Access circuit and method for allowing external test voltage...

Static information storage and retrieval – Interconnection arrangements – Transistors or diodes

Reexamination Certificate

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C365S175000, C365S177000, C365S201000, C257S499000, C257S511000

Reexamination Certificate

active

07027316

ABSTRACT:
An access circuit selectively couples an externally accessible terminal to each of a plurality of isolated DRAM wells in which respective DRAM arrays are fabricated. The access circuit for each well includes first and second transistors fabricated in respective wells coupled between the externally accessible terminal and a respective one of the DRAM wells. The well of the first transistor is coupled to the externally accessible terminal, and the well of the other transistor is coupled to a respective DRAM well. A control circuit applies select signals to gate electrodes of the first and second transistors. The control circuit includes respective shunt transistors that shunt the gate electrodes to the source regions of the first and second transistors when the transistors are turned off to isolate the respective DRAM wells from the external terminal regardless of the magnitude and polarity of a test voltage applied to the externally accessible terminal.

REFERENCES:
patent: 4395723 (1983-07-01), Harari
patent: 6888769 (2005-05-01), Kirsch
patent: 2003/0112659 (2003-06-01), Ohsawa
Favrat, Pierre et al., “A High-Efficiency CMOS Voltage Doubler”, IEEE Journal of Solid-State Circuits, vol. 33, No. 3, Mar. 1998, pp. 410-416.

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