Access arbitration for an input-output controller

Details Access arbitration for an input-output controller Access arbitration for an input-output controller

1990-01-18

1990-09-25

James, Andrew J.

Boots, shoes, and leggings

364900, G06F 1328, G06F 1300

Patent

active

049597825

ABSTRACT:
Arbitration access to an IOC's RAM between the IOC's I/O bus and a signal processor is accomplished by always granting the signal processor access to the IOC's RAM for one machine cycle and disallowing any signal processor operations which would otherwise permit preemptive demand access to memory for more than one machine cycle. The signal processor's activity is then monitored for detecting the signal processor engaged in an activity which does not presently require access to the IOC's RAM and which will occupy the signal processor in a non-memory access activity for a predictable period of time. The IOC's I/O bus is then granted access to the IOC's RAM for a period of time less than the predicted period. In addition to this transparency feature, the present invention may be used in a context of a unique method of transferring data between sensors and actuators on one side of the IOC and the signal processor on the other side. This may be done either according to a default sequence or any one of a plurality of selectable modes of data transfer sequences. The present invention may additionally be used in a redundant channel system for communicating input-output data between channels in blocks in a predefined protocol in which data is transmitted between each channel and all of the channels over cross-channel data links. The blocks are deposited in a portion of link memory partitioned according to the source channel.

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patent: 4716523 (1987-12-01), Burrus, Jr. et al.
patent: 4750113 (1988-06-01), Buggert

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