Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Patent
1990-07-09
1992-11-03
James, Andrew J.
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
257227, 257729, H01L 2906, H01L 2320
Patent
active
051609991
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The invention relates to acceleration resistant packaging for integrated circuits and further relates to a method of producing them.
Normally, integrated circuits are packaged in a plastic or ceramic housing. Depending on the housing type, the terminals are realized in different ways. Customarily bonding wires are brought out from the soldering pads toward the bottom or toward the side. However, circuits packaged in this manner cannot be employed in projectiles. Due to the high accelerations occurring there, microcracks appear in the ceramic housings and, under certain circumstances, the housings are completely destroyed. With plastic housings, bonding wires break off or the plastic material prematurely gasifies so that the required storability does not meet military specifications. Moreover, the prior art packagings frequently require too much space to be used in projectiles.
It has therefore already become known to encapsulate integrated circuits in projectiles or to employ special metal housings.
The encapsulation of circuits, however, has various drawbacks, such as heavy weight, poor testability of the circuit, high temperatures during casting which may cause faults, high expenditures and relatively large structural size, etc.
If metal housings are employed, the resulting structural sizes are also relatively large and costs are high; also, vibration damping is poor.
SUMMARY OF THE INVENTION
It is therefore the object of the present invention to develop an acceleration resistant packaging which has the smallest possible structural size and whose resistance to acceleration is more than 30,000 g. Moreover, vibrations are to be damped and costs justifiable.
This is accomplished according to the invention by an acceleration resistant packaging for integrated circuits wherein: the integrated circuits are each disposed between two thin sheets of a shock resistant, elastic material, wherein connecting leads for the integrated circuits extend beyond the periphery of the thin sheets, and wherein the two thin sheets are fastened together and clamped in a clamping frame along their entire periphery to define a closed interior space containing the integrated circuits.
The basic idea of the invention is thus to employ, for the packaging, not a housing of plastic, ceramic or metal or to encapsulate the circuits, but to arrange the circuits between thin sheets, glue these sheets together and provide them with a clamping frame from which the terminals or connecting leads for the integrated circuit project on the sides.
The thin sheets protect the integrated circuits against environmental influences such as vibrations, radiation and--if the material is selected appropriately--also against temperature fluctuations.
On the basis of the materials employed and their small mass as well as their elasticity, full acceleration resistance is realized in contrast to plastic or ceramic packagings. Moreover, a significant advantage of the packaging according to the invention lies in the great savings in weight and the possibility of accommodating several integrated circuits in one clamping frame.
Greater details and further advantages of the will be described below with reference to embodiments that are illustrated in the drawing figures.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic representation in an exploded view of a packaging according to the invention,
FIG. 2 is a schematic view of the packaging shown in FIG. 1, in the assembled state,
FIG. 3 is a sectional view showing another example of a schematically illustrated packaging according to the invention, with the integrated circuits being arranged in several layers,
FIG. 4 is a sectional view showing the arrangement of the packaging of FIG. 3 in a projectile.
DETAIL DESCRIPTION OF THE PREFERRED EMBODIMENTS
In FIG. 1, the reference numeral 1 identifies a first thin sheet, the numeral 2 a second thin sheet and the reference numerals 3 and 4 identify an upper and a lower frame portion.
Two integrated circuits 5 and 6 are disposed
REFERENCES:
patent: 3152288 (1964-10-01), Mittler
patent: 3221286 (1965-11-01), Fedde
patent: 3376479 (1968-04-01), Wines et al.
patent: 3716846 (1973-02-01), Volckart et al.
patent: 3766439 (1973-10-01), Isaacson
patent: 3772776 (1973-11-01), Weisenburger
patent: 3971127 (1976-07-01), Giguere et al.
patent: 4026011 (1977-05-01), Walton
patent: 4203127 (1980-05-01), Tegge, Jr.
patent: 4412272 (1983-10-01), Wedertz et al.
patent: 4504850 (1985-03-01), Pollard et al.
patent: 4841355 (1989-06-01), Parks
Patent Abstracts of Japan; Band 10, Nr. 179 (E-414) (2235), 24. Jun. 86; & JP, A, 6127663 (NEC Corp.) 7. Feb. 86.
James Andrew J.
Nguyen Viet Q.
Rheinmetall GmbH
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