Acceleration of bitstream decoding

Details Acceleration of bitstream decoding Acceleration of bitstream decoding

2007-10-23

2007-10-23

Young, Brian (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

To or from variable length codes

C341S050000

Reexamination Certificate

active

11303335

ABSTRACT:
Described are methods and systems for variable length decoding. A first execution unit executes a first single instruction that optionally reverses the order of bits in an encoded bitstream. A second execution unit executes a second single instruction that extracts a specified number of bits from the bitstream produced by the first execution unit. A third execution unit executes a third single instruction that identifies a number of consecutive zero bit values at the head of the bitstream produced by the first execution unit. The outputs of the first, second and third execution units are used in a process that decodes the encoded bitstream.

REFERENCES:
patent: 5761466 (1998-06-01), Chau
patent: 6507293 (2003-01-01), Deeley et al.
patent: 6653955 (2003-11-01), Yang
patent: 2004/0143728 (2004-07-01), Flynn et al.

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