Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-04-16
2001-03-27
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189090, C365S226000, C365S204000
Reexamination Certificate
active
06208558
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a non-volatile memory, and more particularly, to an acceleration circuit for fast programming of memory cells in the non-volatile memory.
BACKGROUND ART
Non-volatile memory devices have been developed by the semiconductor integrated circuit industry for various applications such as computers and digital communications. A conventional non-volatile or flash memory device includes a plurality of memory cells typically organized in a plurality of memory sectors. Within each memory sector, the memory cells are arranged in an array comprising a plurality of rows and a plurality of columns. A plurality of word lines are coupled to the respective rows of the memory cells, and a plurality of bit lines are coupled to the respective columns of the memory cells. Each of the memory cells may be a typical binary dual-gate NOR device, for example, which comprises a source, a drain and a gate. Each memory cell is capable of storing one bit. During the operation of a conventional non-volatile memory, a memory cell is either programmed or erased by supplying a pump voltage to either the drain or the source of the memory cell, depending upon whether the non-volatile memory is in a conventional embedded program mode or in a conventional embedded erase mode.
When the memory cells are in a conventional embedded program mode, it is usual that more than one bit and sometimes all of the bits need be programmed on each of the word lines. For example, if a memory sector comprises a 16-bit words, then a row of sixteen memory cells are disposed on each word line, and sixteen bit lines are connected to the sixteen memory cells, respectively.
In a conventional embedded program mode, a pump current is supplied to the drain of each memory cell to be programmed. A conventional internal drain pump is typically capable of supplying only a limited amount of total pump current to some but not all of the bit lines simultaneously. For example, in conventional programming of flash memory cells comprising typical dual-gate NOR devices, wherein each NOR gate stores either bit “
0
” upon being “programmed” or bit “
1
” being “erased”, a pump current typically on the order of about 0.5 mA need be provided to the drain of each memory cell to be programmed with bit “
0
” through the respective bit line.
However, a conventional internal pump with a typical voltage supply of 3 V or lower is typically limited in its capability to supplying pump currents to the drains of no more than five of the memory cells at a time. In order to program a 16-bit word, for example, sixteen columns of memory cells on sixteen bit lines are grouped into four sets, each set comprising four columns. When the memory cells are programmed in a conventional embedded program mode, the conventional internal pump provides pump currents through the respective bit lines to program the memory cells one set of columns at a time. For example, a typical 16-bit word with bits numbered 0-15 may be grouped into four sets of bits numbered
0
-
3
,
4
-
7
,
8
-
11
and
12
-
15
. When any set of four bits are to be programmed with up to four zeroes, this arrangement ensures that a sufficient pump current is supplied to the drain of each of the memory cells through the respective bit line. When the memory cells are in a conventional embedded chip erase mode, the conventional internal pump has similar limitations in that it is capable of erasing the memory cells by supplying a source voltage to the sources of only one set of memory cells at a time.
Because the conventional internal pump has a limited current supply and is typically capable of programming or erasing the memory cells on the bit lines only one set at a time, it takes a plurality of pulses generated by the internal pump to be supplied to different sets of bit lines during the programming or erase of each word along each word line. Moreover, the power from the internal pump need be switched to different sets of bit lines during the programming or erase of each word. Therefore, programming and erasing of a whole sector of memory cells can be time consuming in the conventional embedded program and erase modes.
Therefore, there is a need for an acceleration circuit for fast programming and fast chip erase of the memory cells in a non-volatile memory. Furthermore, there is a need for a method of programming the memory cells in the non-volatile memory to increase the speed of programming over that which is achieved by the conventional embedded programming mode. There is yet a further need for a method of erasing the memory cells with an increased speed over that which is achieved by the conventional embedded chip erase mode.
DISCLOSURE OF THE INVENTION
The present invention satisfies these needs. In accordance with the present invention, an acceleration circuit for fast programming of memory cells in a non-volatile memory generally comprises:
(a) an acceleration input capable of providing an acceleration voltage to supply a current for programming the memory cells on all of the bits lines at a time for any particular word in a fast program mode, the acceleration voltage being greater than the internal pump voltage supplied by the conventional internal voltage supply pump; and
(b) a triggering circuit, coupled to the acceleration input, capable of disabling the conventional internal voltage supply pump and causing the acceleration voltage to be supplied to the memory cells on all of the bit lines at a time in response to a presence of the acceleration voltage at the acceleration input.
In an embodiment, the acceleration input comprises an acceleration pin capable of receiving the acceleration voltage from a source external to the non-volatile memory. In an embodiment, the triggering circuit comprises a high voltage detector, coupled to the acceleration input, capable of generating an acceleration voltage indicator signal in response to a presence of the acceleration voltage at the acceleration input. In a further embodiment, the triggering circuit comprises a program command write input capable of receiving a program command, and a logic circuit, coupled to the high voltage detector and the program command write input, capable of generating a fast program command in response to the acceleration voltage indicator signal and the program command. In yet a further embodiment, the triggering circuit further comprises an erase command write input capable of receiving an erase command, and the logic circuit has an additional output capable of generating a fast chip erase command.
In an embodiment, the acceleration circuit according to the present invention further comprises a regulator, coupled to the acceleration input, capable of regulating the acceleration voltage to generate an appropriate voltage to program the memory cells selected to be programmed in the fast program mode. In a further embodiment in which the memory cells are in the fast program mode, the acceleration input is further capable of supplying the acceleration voltage unregulated as a gate voltage for the memory cells on the word line selected to be programmed. In an embodiment in which each memory cell comprises a typical dual-gate NOR device, the acceleration voltage is in the range of about 7 V to about 10 V, and the regulated drain voltage is on the order of about 5 V.
In an additional embodiment, the acceleration circuit according to the present invention is also capable of supplying a regulated source voltage to the sources of the memory cells in a fast chip erase mode. In an embodiment in which the memory cells are in the fast chip erase mode, a fast preprogramming operation, a fast erase operation and a fast weak programming operation are performed sequentially on the memory cells. The fast weak programming operation is also called a fast APDE operation.
The initial fast preprogramming operation in the fast chip erase mode can be performed as if the memory cells are in the fast programming mode, by applying the regulated acceleration voltage to the drains of the memory cells. During the fast
Chen Johnny
Kuo Tiao-Hua
Leong Nancy
Advanced Micro Devices , Inc.
Auduong Gene N.
Fliesler Dubb Meyer & Lovejoy LLP
Nelms David
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