Accelerated validity response permitting early issue of instruct

Details Accelerated validity response permitting early issue of instruct Accelerated validity response permitting early issue of instruct

1986-08-15

1989-07-04

Williams, Jr., Archie E.

Boots, shoes, and leggings

3649371, 3649378, G06F 1500, G06F 1520, G06F 1531, G06F 1532

Patent

active

048456594

ABSTRACT:
Apparatus and method for accelerating a validity response provided by a floating point unit assures the validity of the present state of a condition code and an interrupt signal before the completion of a floating point arithmetic instruction whose result affects the condition code and interrupt signal. The accelerated validity response is derived from an evaluation of the exponents, signs, and fractions contained in the operands of a currently-executing floating point arithmetic operation which is made prior to or during execution of the instruction. Also provided is the capability of setting the condition code prior to the completion of certain add class floating point instructions where one of those instructions stimulates an early validity response. An accelerated interrupt request is also provided in synchronism with an accelerated validity response for certain floating point add and subtract instructions.

REFERENCES:
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patent: 4542456 (1985-09-01), Hill
patent: 4573118 (1986-02-01), Damouny et al.
patent: 4683546 (1987-07-01), Boney
"The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling", by D. W. Anderson et al., IBM Journal, Jan. 1967.
"An Efficient Algorithm for Exploiting Multiple Arithmetic Units", by R. M. Tomasulo, IBM Journal, Jan. 1967.
"The IBM System/360 Model 91: Floating-Point Execution Unit", by S. F. Anderson et al., IBM Journal, Jan. 1967.

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