Accelerated thermal stress cycle test

Details Accelerated thermal stress cycle test Accelerated thermal stress cycle test

2001-10-11

2003-08-12

Gutierrez, Diego (Department: 2859)

Thermal measuring and testing

Thermal testing of a nonthermal quantity

Of susceptibility to thermally induced deteriouration, flaw,...

C374S005000, C073S865600, C324S760020

Reexamination Certificate

active

06604853

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to a reliability test for semiconductor chips and more particularly, relates to an accelerated thermal stress cycle test for semiconductor chips.
BACKGROUND OF THE INVENTION
In semiconductor fabrication technologies, the reliability test conducted on the semiconductor chips fabricated is an important part of the total fabrication process. One of such reliability tests is the thermal stress cycle test or the thermal voiding test.
In a thermal stress cycle test, the stress experienced by a metallic thin film that played a critical role in the stability of fine line interconnects is tested. The thermal stress cycle test can reveal the thermal voiding defect which is a major problem in passivated copper or aluminum metalization, especially when deposited on stiff dielectrics such as sputtered SiO
2
or SiN
x
. Conventionally, metallic films such as copper or aluminum used as interconnections are subjected to many thermal cycles between room temperature and 400° C., during various processes of deposition, lithography and etching. Since the deposition temperatures for the dielectric insulators may exceed 300° C., some but not all of the film stress can be relieved. For instance, commonly used inorganic insulators such as PECVD oxide, APCVD oxide and nitrides are deposited at temperatures in the range between 300° C. and 500° C. When these deposited insulators are cooled down, the rigid insulators restrict the ability of the metal films to relax thermal stresses imposed on them.
It is known that the driving force for the thermal stress problem is the thermal expansion mismatch between the metal films and the insulating dielectric materials that enclose the films and the silicon substrate. It is theorized that thermal stress-induced failure is caused by the confinement of the copper or aluminum lines or films by the dielectric insulators which have thermal expansion coefficients smaller than that of copper or aluminum. Conventionally, a thermal voiding defect or a metal film peeling defect is studied by thermal cycle samples to a high temperature where grain boundary diffusion is rapid and the stress in the film is close to zero. The sample is typically cycled between room temperature and a high temperature, i.e., between 300° C. and 500° C., and examined periodically for signs of void nucleation or growth and for metal film peeling.
Another reliability test that is frequently conducted simultaneously with the thermal stress cycle test is the thermal shock testing. The objective of thermal shock testing is somewhat similar to that for the thermal stress cycle test. However, the thermal shock test provides additional stress since the device is exposed to a sudden change in temperature due to the rapid rate of temperature change. Failure mechanisms which are caused by temperature transients and temperature gradients can be detected by the thermal shock test. The test can be conducted by either a rapid temperature increase, or a rapid temperature decrease, or by cycling through both. The test is normally conducted for a predetermined number of cycles to detect common failure modes which include parametric shifts and catastrophic events. The common failure mechanisms observed may include wirebond cracked, dies lifted and package failure.
Conventionally, the thermal stress cycle test and the thermal shock test are conducted in a furnace for a predetermined number of cycles. Since a furnace has a large volume and therefore requires a long time for heating or cooling, it is not unusual to require three or four hours for conducting a single thermal cycle between room temperature and a high temperature, i.e. between 300° C. and 500° C. When such furnace cycle test is conducted, even at a minimum of three cycles, a total test time of at least 12 hours is required. The conventional thermal cycle/thermal shock test therefore is a time consuming task which cannot be easily conducted in a timely manner.
It is therefore an object of the present invention to provide a thermal stress cycle test method that does not have the drawbacks or shortcomings of the conventional thermal stress cycle test.
It is another object of the present invention to provide a thermal stress cycle test that does not require the use of a conventional furnace for conducting the test.
It is a further object of the present invention to provide a thermal stress cycle test that can be conducted in a significantly shorter time period when compared to a conventional thermal stress cycle test.
It is another further object of the present invention to provide a thermal stress cycle test and a thermal shock test which can be conducted together.
It is still another object of the present invention to provide a thermal stress cycle test in a cluster of test chambers that includes a heating chamber and a cooling chamber.
It is yet another object of the present invention to provide a thermal stress cycle test wherein the test can be conducted with a 85% reduction in the required test time when compared to a conventional thermal stress cycle test.
It is still another further object of the present invention to conduct a thermal stress cycle test in a chemical vapor deposition chamber for heating and in a cool-down chamber for cooling.
SUMMARY OF THE INVENTION
In accordance with the present invention, an accelerated thermal stress cycle test for the reliability testing of semiconductor chips is provided.
In a preferred embodiment, an accelerated thermal stress cycle test can be carried out by the operating steps of providing a cluster of reaction chambers including at least one chemical vapor deposition (CVD) chamber and at least one cool-down chamber; heating a pre-processed wafer by positioning the wafer in the at least one CVD chamber to at least 350° C. in an inert gas environment for at least 2 min.; cooling the pre-processed wafer by moving from the at least one CVD chamber to the at least one cool-down chamber to a temperature not higher than 70° C.; repeating sequentially the heating and cooling step for at least three times; and determining any defect caused by the repeated heating and cooling steps.
In the accelerated thermal stress cycle test, the cluster of reaction chambers may have a LPCVD chamber and a cool-down chamber, the at least one CVD chamber may be a single wafer LPCVD chamber that includes heating lamps, the at least one CVD chamber is a single wafer LPCVD chamber that includes heating means capable of heating a wafer from 23° C. to 350° C. within 2 min. The at least one CVD chamber is a single wafer LPCVD chamber that includes heating means for heating a wafer from 20° C. to 350° C. within 2 min. in an inert gas environment, such as in N
2
, He or Ar. The test method may further include the step of moving the pre-processed wafer from the at least one CVD chamber to the at least one cool-down chamber by a robot blade. The method may further include the step of cooling down the pre-processed wafer from at least 350° C. to not higher than 70° C. in a time period of not less than 30 sec. The method may further include the step of repeating sequentially the heating and cooling steps between 3 and 10 times, or preferably between 4 and 7 times.
The present invention is further directed to a thermal stress cycle test that can be carried out by the operating steps of providing a heating chamber and a cooling chamber positioned juxtaposed to each other; positioning a pre-processed wafer in the heating chamber and heating the pre-processed wafer from 23° C. to at least 350° C. in less than 2 min.; positioning the pre-processed wafer in the cooling chamber and cooling the wafer from 350° C. to not higher than 70° C. in less than 30 sec.; repeating sequentially the heating and cooling steps for at least 3 times; and determining any defect formed on the pre-processed wafer.
The method for thermal stress cycle test may further include the step of transporting the pre-processed wafer from the heating chamber to the cooling chamber by a robot blade. The method may further i

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