Accelerated testing method and circuit for non-volatile memory

Details Accelerated testing method and circuit for non-volatile memory Accelerated testing method and circuit for non-volatile memory

2001-08-14

2002-09-03

Elms, Richard (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S201000

Reexamination Certificate

active

06445614

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90118848, filed Aug. 2, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a testing circuit and testing method for a non-volatile memory. More particularly, the present invention relates to an accelerated testing method and circuit for a non-volatile memory having a trapping layer therein.
2. Description of Related Art
In general, each memory cell in a non-volatile memory such as a flash ROM has a gate structure that includes a control gate and a floating gate. The control gate receives a control voltage for controlling the action of the cell and the floating gate is a place for holding electric charges. Because the floating gate is normally made from conductive polysilicon material, any electrons injected into the floating gate will spread out evenly throughout the layer when the memory cell is programmed. Consequently, each memory cell having such as floating gate structure can store only a single bit. In a later version, insulating material is used to form the floating gate in the memory cell structure. Since the insulating material is able to constrain movement of electric charges, electrons can be localized resulting in the possibility of holding two bits in each cell. Ultimately, capacity of each memory cell is increased.
FIG. 1
is a schematic cross-sectional view showing a conventional non-volatile memory cell having a trapping layer that can hold two bits of data. As shown in
FIG. 1
, the substrate contains ion-doped regions that serve respectively as a source terminal
18
and a drain terminal
16
of the memory cell. A gate structure is formed over the substrate. The gate structure is a stack that includes an oxide layer
10
, a nitride layer
12
and another oxide layer
14
. The nitride layer
12
is a trapping layer for retaining electrons. Here, channel hot electron injection and band-to-band hot hole injection mechanism is utilized to program data into the memory cell or to erase data from the memory cell.
Since the trapping layer
12
is a non-conductive layer (an isolation layer), electrons induced into the trapping layer
12
are localized in regions close to the side having a drain or a source terminal nearby. In other words, when a programming voltage is applied to the gate electrode and the drain electrode while a 0V is applied to the source electrode, a strong electric field is created between the gate and the drain. Electrons are attracted into the trapping layer near the drain terminal and trapped there. Conversely, when a programming voltage is applied to the gate electrode and the source electrode while a 0V is applied to the drain terminal, a strong electric field is created between the gate and the drain. Electrons are attracted into the trapping layer near the source terminal and trapped there. Through the application of these two voltage settings, two bits of data are stored in each memory cell. In
FIG. 1
, locations for holding the first bit
1
and the second bit
2
are indicated.
TABLE ONE
V
g
(V)
V
s
(V)
V
d
(V)
V
b
(V)
Program
Bit 1
10
4
0
0
Bit 2
10
0
4
0
Erase
Bit 1
−3
+5
floating
0
Bit 2
−3
floating
+5
0
Read
Bit 1
2.75
0
1.6
0
Bit 2
2.75
1.6
0
0
For this type of memory cell, threshold voltage V, of the memory cell is changed by the injection of electrons into the trapping layer
12
. However, the threshold voltage will drop as retention time is increased after each program/erase (P/E) cycle. The dropping of threshold voltage leads to an increase in leakage current and a loss of memory data. For example, if a voltage greater than a specific threshold voltage represents the logic state “0”, actual state will be indistinguishable due to a drop in threshold voltage. In other words, stored data within the memory cell cannot be accurately read.
To ensure the long-term reliability of memory products in the hands of customers, the memory cells are tested so that even if the threshold voltage drops after a long retention period, the memory cell still manages to operate within a normal operating range without failure. Nevertheless, due to the limited testing period, a testing method for accurately determining the effective lifetime of memory cells becomes a major issue.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide an effective testing method and installation that utilizes characteristic physical properties of a non-volatile memory having an insulating trapping layer therein to determine long term reliability of the memory. The method involves an accelerated testing capable of estimating future lifetime of the memory within a short test period.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides an accelerated testing method. A threshold voltage variation standard is chosen. A set of negative gate bias voltage is applied to the gate terminal of the non-volatile memory to conduct an accelerated test and obtain a test result. According to the test result, a curve showing the relationship between lifetime and negative gate bias voltage is obtained. Finally, according to the threshold voltage variation standard, lifetime of the non-volatile memory is determined.
This invention also provides a testing circuit for assessing the quality of memory cell array within a non-volatile memory. The memory cell array contains a plurality of memory cells arranged to form a plurality of rows and columns. Each row is coupled to a word line driver while each column is coupled to a bit line bias voltage circuit. The non-volatile memory quality testing circuit includes a word line negative gate bias voltage generator coupled to the word line driver for applying a set of negative gate bias voltages to the gate of a programmed memory cell and conducting an accelerated testing.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5636168 (1997-06-01), Oyama
patent: 5793675 (1998-08-01), Cappelletti et al.
patent: 5901080 (1999-05-01), Shouno
patent: 6128219 (2000-10-01), Pio et al.

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