Accelerated test apparatus and support logic for a content addre

Details Accelerated test apparatus and support logic for a content addre Accelerated test apparatus and support logic for a content addre

1985-08-05

1987-07-14

Fleming, Michael R.

Excavating

371 11, G06F 100

Patent

active

046807608

ABSTRACT:
Accelerated test circuitry and support logic to test a content addressable memory (CAM). In a CAM array of n entries of m bits per entry, the testing of each word lind, each memory element, each exclusive OR (XOR) comparator and each match line may be thoroughly and quickly tested by means of the parallelism inherent in a CAM array and by the addition of a bulk load mechanism to enable all of the word lines simultaneously. The further addition of an ALLHIT indicator to assess all of the match lines in a single operation also reduces the number of operations and simplifies the test algorithm. The ALLHIT indicator may be an AND gate or a scan path.

REFERENCES:
patent: 3800286 (1974-03-01), Brown
patent: 4377855 (1983-03-01), Lavi
patent: 4532606 (1985-07-01), Phelps
patent: 4559618 (1985-12-01), Houseman
J. T. Koo, "Integrated Circuit Content-Addressable Memories", IEEE Journal of Solid-State Circuits, vol. SC-5, No. 8, Oct., 1970, pp. 208-215.
T. Ogura, et al., "A 4-Kbit Associative Memory LSI", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 6, Dec., 1985, pp. 1277-1282.

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