Accelerated prime sieving using architecture-optimized...

Details Accelerated prime sieving using architecture-optimized... Accelerated prime sieving using architecture-optimized...

2008-04-24

2009-06-23

Mai, Tan V (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C380S028000

Reexamination Certificate

active

07552164

ABSTRACT:
This embodiment teaches a variation of GCD-based sieving, building tables of prime products, but intentionally restricting the size of table entries to fit within a single machine word. This combination allows one to mix advantages of the two most popular sieves, while retaining the simple and straightforward structure of the simpler one. Divisor length restriction can provide significant savings in the number of long divisions, but may be implemented with only two very specific primitives. The two primitives offer better optimization capabilities than a fully generic multiword arithmetic library.

REFERENCES:
patent: 7120248 (2006-10-01), Hopkins et al.
patent: 2002/0174155 (2002-11-01), Hars et al.
patent: 2005/0027764 (2005-02-01), Agrawal et al.
patent: 2007/0112818 (2007-05-01), Sastry
patent: 2009/0006512 (2009-01-01), Ozturk et al.
patent: 00449349 (1994-04-01), None
patent: WO0108350 (2001-02-01), None
patent: WO04001595 (2003-12-01), None

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