Accelerated mode tester timing

Details Accelerated mode tester timing Accelerated mode tester timing

1996-08-13

1997-09-30

Canney, Vincent P.

Excavating

G06F 1100

Patent

active

056732759

ABSTRACT:
A test system, for testing circuits, having two operating modes, a normal mode and an accelerated mode. The test system has a first start memory, a second start memory, a first sequence memory, and a second sequence memory. The start memories provide sequence memory addresses for addressing the sequence memories, and the sequence memories provide event sequences in response to sequence memory addresses. If operating in normal mode, the start memories are electronically coupled (switched) to provide a single sequence memory address to both sequence memories. If operating in accelerated mode, the start memories are electronically coupled so that the first start memory provides a first sequence memory address to the first sequence memory and the second start memory provides an independent second sequence memory address to the second sequence memory. In particular embodiments, the first and second start memories are of the same size, the first and second sequence memories are of the same size, and the sequence memories produce a word including at least two events in response to a sequence memory address. In a further embodiment, the test system has three operating modes: normal, accelerated, and double-accelerated. For the double-accelerated mode, four start memories and four sequence memories are provided.

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