Accelerated graphics port multiple entry gart cache allocation s

Details Accelerated graphics port multiple entry gart cache allocation s Accelerated graphics port multiple entry gart cache allocation s

1997-09-30

1999-09-07

Chauhan, U.

Computer graphics processing and selective visual display system

Computer graphic processing system

345520, 711118, 711202, G06F 1500, G06T 100

Patent

active

059494360

ABSTRACT:
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory. The core logic chipset may cache a subset of the most recently used GART table entries to increase AGP performance when performing the address translation. When a GART table entry is not found in the cache, a memory access is required to obtained the needed GART table entry. There are two GART table entries in each quadword returned in toggle mode of the cacheline of memory information returned from the memory read access. At least one quadword (two GART table entries) are stored in the cache each time a memory access is required because of a cache miss.

REFERENCES:
patent: 5479627 (1995-12-01), Khalidi et al.
patent: 5546555 (1996-08-01), Horstmann et al.
patent: 5664161 (1997-09-01), Fukushima et al.
patent: 5812789 (1998-09-01), Diaz et al.
Beckert, B., "HP Systems", Computer-Aided Engineering; vol. 16, Nov. 1997, p22, 2p.
Blackwood, J. et al., "Monster MMX Machines|", Windows Magazine, vol. 8, Feb. 1, 1997, p96, 11p.
Forbes, J., "Port in the 3-D Storm", Windows Magazine, vol. 8, May 1, 1997, p198, 2p.
Santoni, A., "Intel Lays Out the Road to Katmai", InfoWorld, Dec. 1, 1997, vol. 19, p6.
Brummer, Robert, "PCI-to-AGP Move Boosts 3-D Graphics", Electronic Engineering Times, May 5, 1997, n952, p. 84.
Yao, Yong, "AGP Speeds 3D Graphics", Microprocessor Report, Jun. 17, 1996, v10 n8, p. 11(5).
Halfhill, Tom, "Unclogging the PC Bottlenecks", BYTE, Sep. 1997, vol. 22, No. 9 p. 80NA1.
Accelerated Graphics Port Interface Specification, Revision 1.0, Intel Corporation, Jul. 31, 1996.

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