Accelerated graphics port memory mapped status and control regis

Details Accelerated graphics port memory mapped status and control regis Accelerated graphics port memory mapped status and control regis

1997-09-30

1999-08-10

Chauhan, U.

Computer graphics processing and selective visual display system

Computer graphic processing system

345516, 345512, 395280, 395309, 395874, G06F 1500, G06F 1206

Patent

active

059366400

ABSTRACT:
A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. A plurality of AGP memory-mapped status and control registers are stored in the computer system memory, and are used for status and control of AGP functions in the computer system.

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