Accelerated data transfer mechanism using modified clock cycle

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3642702, 3642703, 3642709, 36424341, G06F 104, G06F 1300

Patent

active

049530771

ABSTRACT:
A data processing system having a first logical device capable of sending and receiving clocked electronic data and a second logical device connected to the first logical device, the second logical device also being capable of sending and receiving clocked electronic data. A controller is connected to the first and second logical devices for controlling data transfer therebetween. The controller includes a clock edge generator and gating logic connected thereto for allowing the first logical device to accept data and the second logical device to send data during a time interval of an odd number of clock edges.

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Pitkowsky et al. "Data Processing System Clock Control" IBM Tech. Discl. Bull., vol. 7, No. 9, Feb. 1965, pp. 754-755.
Maholick, A. "Ternary Logic Memory Elements" IBM Tech. Disc. Bull., vol. 26, no. 3A, Aug. 1983, pp. 1196-1197.

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