AC timing asymmetry reduction circuit including summing DC offse

Details AC timing asymmetry reduction circuit including summing DC offse AC timing asymmetry reduction circuit including summing DC offse

1993-12-17

1995-11-21

Psitos, Aristotelis

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Data clocking

360 68, G11B 509, G11B 503

Patent

active

054693055

ABSTRACT:
A DC offset voltage is added to the analog timing signal in a peak detection data recovery circuit to cancel the timing asymmetry from a magnetoresistive head signal. An AC timing asymmetry cancellation circuit uses a charge pump, buffer amplifier and resistor divider to produce the proper DC offset voltage automatically.

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"Integrating An MR Head Into A Peak Detection Channel", Nathan Curland and Russell J. Machelski.

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