AC interconnect test of integrated circuit chips

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371 221, G01R 3128

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054447151

ABSTRACT:
An integrated circuit chip (110) adapted to provide interconnect capability and an AC interconnect test method therefor. Test and control data are scanned in the scan-path of latches (114 and 115) to initialize the AC interconnect test. Subsequently the functional system mode is simulated by applying the functional-system clocks via lines (118 and 128).

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C. Maunder, et al., "Boundary-Scan A Framework for Structured Design-for-Test" International Test Conference Proceedings, pp. 714-723, 1987.
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"AC Interconnect Test with Series Boundary Scan" IBM Technical Disclosure Bulletin, V. 34, No. 6, pp. 325-330, Nov. 1991.

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