Abstract verification environment

Details Abstract verification environment Abstract verification environment

2005-02-15

2005-02-15

Broda, Samuel (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

C703S015000, C703S020000, C703S022000, C714S741000, C714S742000

Reexamination Certificate

active

06856950

ABSTRACT:
A system and method of verifying an electronic system. A verification kernel is provided and the electronic system is expressed as a logic design. A wrapper is defined, wherein the wrapper is an interface between the logic design and the verification kernel. Tests to be run against the logic design are placed within a diagnostic program and an interface between the diagnostic program and the verification kernel is defined. The tests are then executed against the logic design. The results of the tests are captured and validated against expected results.

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