Communications: electrical – Digital comparator systems
Patent
1993-04-08
1994-12-27
Heyman, John S.
Communications: electrical
Digital comparator systems
377 33, 326105, G06F 702
Patent
active
053769155
ABSTRACT:
Disclosed is an absolute value comparator for comparing respective absolute values of sequentially applied two data. A decoder circuit sequentially converts the applied data into a plurality of bit signals in accordance with a predetermined rule. After a preceding conversion bit signal is once held in a register circuit, the held bit signal is inverted for each bit by an inversion circuit. Thus, a logic circuit receives a preceding inverted bit signal and a succeeding conversion bit signal and outputs an output signal B indicating the result of comparison. Since a full adder is unnecessary, a comparison between the absolute values of the applied data can be made at a high speed.
REFERENCES:
patent: 3942171 (1976-03-01), Haraszti et al.
patent: 4344005 (1982-08-01), Stewart
patent: 4429238 (1984-01-01), Harrison
patent: 4471310 (1984-09-01), Yenisey
patent: 5034630 (1991-07-01), Sugiyama et al.
Ito Masao
Takeuchi Sumitaka
Heyman John S.
Mitsubishi Denki & Kabushiki Kaisha
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