Pulse or digital communications – Synchronizers – Frequency or phase control using synchronizing signal
Reexamination Certificate
1999-12-22
2004-01-13
Chin, Stephen (Department: 2634)
Pulse or digital communications
Synchronizers
Frequency or phase control using synchronizing signal
C375S354000, C375S371000
Reexamination Certificate
active
06678342
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an absolute-phasing synchronization capturing circuit, and more particularly to an absolute-phasing synchronization capturing circuit for absolute-phasing a received signal phase angle to make it coincide with a transmission signal phase angle, the circuit being used with a receiver which receives a digital signal modulated by different modulation methods having different necessary C/N.
BACKGROUND OF THE INVENTION
In a broadcasting receiver which receives a modulated digital signal transmitted by a hierarchical transmission method with a time sequential combination of different modulation methods having different necessary C/N, such as 8PSK modulation, QPSK modulation and BPSK modulation, to be repeated for each frame, an absolute-phasing synchronization capturing circuit absolute-phases a received signal phase angle to make it coincide with a transmission signal phase angle, by capturing a frame synchronization signal from demodulated baseband signals (hereinafter also called a symbol stream), by calculating a current received signal phase rotation angle from the signal point arrangement of the captured frame synchronization signal, and by rotating the demodulated baseband signals in a reverse phase direction in accordance with the calculated received signal phase rotation angle.
A conventional absolute-phasing synchronization capturing circuit has, as shown in
FIG. 14
, a demodulation circuit
1
, a frame synchronism detection block
2
, a frame synchronization signal generator
6
, a remapper
7
made of a ROM, and a received signal phase detection block
8
. The frame synchronism detection block
2
has a BPSK demapper
3
, synchronism detection circuits
40
to
47
, and a frame synchronization circuit
5
. The received signal phase detection block
8
has delay circuits
81
and
82
, a 0°/180° phase rotation circuit
83
, accumulating/adding/averaging circuits
85
and
86
, and a received signal phase determining circuit
87
.
The conventional absolute-phasing synchronization capturing circuit shown in
FIG. 14
frequency-converts a received digital modulated signal into a signal having a predetermined intermediate frequency which is supplied to the demodulation circuit
1
to demodulate the intermediate frequency signal. The demodulation circuit
1
outputs demodulated baseband signals, e.g., baseband signals I(
8
) and Q(
8
) with the quantization bit number of
8
(numerals in the parentheses indicate the number of bits which are sometimes omitted in the following and simply written as I and Q).
The baseband signals I(
8
) and Q(
8
) are input to, for example, the BPSK demapper
3
of the frame synchronism detection block
2
in order to capture the BPSK modulated frame synchronization signal. The BPSK demapper
3
outputs a BPSK demapped bit stream B
0
. The BPSK demapper
3
is made of, for example, a ROM.
Mapping for each modulation method on the transmission side will be described with reference to FIG.
15
. FIG.
15
(
a
) shows a signal point arrangement for 8PSK modulation. 8PSK modulation can transmit a three-bit digital signal (a, b, c) by one symbol. There are eight combinations of bits constituting one symbol, i.e., (0, 0, 0), (0, 0, 1), . . . , (1, 1, 1). These 3-bit digital signals are converted into signal point arrangements
0
to
7
on a transmission side I-Q vector plane shown in FIG.
15
(
a
). This conversion is called 8PSK mapping.
In the example shown in FIG.
15
(
a
), a bit train (0, 0, 0) is converted into the signal point arrangement “
0
”, a bit train (0, 0, 1) is converted into the signal point arrangement “
1
”, a bit train (0, 1, 1) is converted into the signal point arrangement “
2
”, a bit train (0, 1, 0) is converted into the signal point arrangement “
3
”, a bit train (1, 0, 0) is converted into the signal point arrangement “
4
”, a bit train (1, 0, 1) is converted into the signal point arrangement “
5
”, a bit train (1, 1, 1) is converted into the signal point arrangement “
6
”, and a bit train (1, 1, 0) is converted into the signal point arrangement “
7
”.
FIG.
15
(
b
) shows a signal point arrangement for QPSK modulation. QPSK modulation can transmit a two-bit digital signal (d, e) by one symbol. There are four combinations of bits constituting one symbol, i.e., (0, 0), (0, 1), (1, 0) and (1, 1). In the example shown in FIG.
15
(
b
), a bit train (1, 1) is converted into the signal point arrangement “
1
”, a bit train (0, 1) is converted into the signal point arrangement “
3
”, a bit train (0, 0) is converted into the signal point arrangement “
5
”, and a bit train (1, 0) is converted into the signal point arrangement “
7
”. The relation between the signal point arrangement and its number of each modulation method is defined in the same manner as 8PSK modulation.
FIG.
15
(
c
) shows a signal point arrangement for BPSK modulation. BPSK modulation can transmit a one-bit digital signal (f) by one symbol. The digital signal (
1
) is converted into the signal point arrangement “
0
” and the digital signal (
0
) is converted into the signal point arrangement “
4
”.
Next, the frame synchronization signal will be described. In the hierarchical transmission method, the frame synchronization signal modulated by BPSK having the lowest necessary C/N is transmitted. It is assumed herein that the bit stream of the frame synchronization signal constituted of 16 bits is (S
0
, S
1
, . . . , S
14
, S
15
) and each bit is transmitted starting from S
0
. In this case, a bit stream (0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0) and a bit stream with inverted last half eight bits (0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1) are alternately transmitted for each frame. In the following, the bit stream of the frame synchronization signal is also written as “SYNCPAT”, and the bit stream with inverted last half eight bits is also written as “nSYNCPAT”. At transmission side this bit stream is converted into either the signal point arrangement “
0
” or “
4
” by BPSK mapping shown in FIG.
15
(
c
), and the converted symbol stream is transmitted.
In order to capture the frame synchronization signal of 16 bits, i.e., 16 symbols BPSK-modulated and transmitted, the received symbols are required to be converted into bits by BPSK demapping shown in FIG.
16
(
a
) opposite to the mapping at the transmission side. As shown in FIG.
16
(
a
), if the demodulated signal is received in a hatched area on the reception side I-Q vector plane, it is judged as “
1
”, whereas if it is received in an area not hatched, it is judged as “
0
”. Namely, depending upon whether the demodulated signal is received on which area among the two areas divided by a bold BPSK determining borderline of FIG.
16
(
a
), the output is judged as “1” or “0”. This operation is called BPSK demapping.
The baseband signals I and Q are input to the BPSK demapper
3
to perform the bit conversion. The BPSK demapper
3
performs BPSK demapping and outputs a bit stream B
0
. In this specification, the term “demapper” means a demapping circuit. The bit stream B
0
is input to the synchronism detection circuit
40
which captures the bit stream of the frame synchronization signal from the bit stream B
0
.
Next, the synchronism detection circuit
40
will be described with reference to FIG.
17
. The bit stream B
0
is input to a shift register D
15
and sequentially shifted up to a shift register D
0
. At the same time, after the logical levels of the outputs of the shift registers D
15
to D
0
at predetermined bits are inverted, the outputs of the shift registers D
15
to D
0
are input to AND gates
51
and
52
. An output SYNA
0
of the AND gate
51
takes a high level when the status of the shift registers D
15
to D
0
(D
0
, D
1
, . . . , D
14
, D
15
) becomes (0, 0, 0, 1, 0, 0, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0), whereas an output SYNB
0
of the AND gate
52
takes a high level when the status becomes (0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0, 0, 1). Namely, when SYNCPAT is captured, the output SYNA
0
takes the high level, and when nSYNCPAT is
Horii Akihiro
Shiraishi Kenichi
Chin Stephen
Kabushiki Kaisha Kenwood
Odom Curtis
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
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