Boots – shoes – and leggings
Patent
1994-09-14
1997-03-11
Mai, Tan V.
Boots, shoes, and leggings
36471501, G06F 750
Patent
active
056108508
ABSTRACT:
The absolute difference calculation circuits 101 through 10N each consisting of a subtractor which calculates the difference of two numbers each consisting of i bits and a bit inversion selector circuit which-provides the result of subtraction as it is when no borrow output is produced by the subtractor, and inverts every bit of the result of subtraction when there is a borrow output, to obtain 1's complement of the absolute value of difference. The multiple input adder 2 receives the borrow as input to the least significant bit thereof and adds the result of each absolute difference calculation circuit. Because the adding operations to obtain 2's complement in the absolute difference calculation circuit are carried out together in the multiple input adder that follows, number of adders required to calculate the absolute value of difference can be greatly reduced and the amount of entire circuitry can be greatly reduced.
REFERENCES:
patent: 4761759 (1988-08-01), Nakagawa
patent: 4908788 (1990-03-01), Fujiyama
patent: 4953115 (1990-08-01), Kanoh
patent: 5040136 (1991-08-01), Kanoh
patent: 5216628 (1993-06-01), Mizutani et al.
"A Floating-Point Cell Library and a 100 Mflops Digital Signal Processor", by C. Hori et al, Electric Information Communication Institution, Technological Search Report, pp. 97-104, Mar. 6, 1992.
Kitaura Aoi
Uratani Munehiro
Mai Tan V.
Sharp Kabushiki Kaisha
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