Abridged virtual address cache directory

Details Abridged virtual address cache directory Abridged virtual address cache directory

1994-04-26

1998-05-12

Swann, Tod R.

395403, 395445, G06F 1208

Patent

active

057519900

ABSTRACT:
A hierarchical memory utilizes a translation lookaside buffer for rapid recovery of virtual to real address mappings and a cache system. Lines in the cache are identified in the cache directory by pointers to entries in the translation lookaside buffer. This eliminates redundant listings of the virtual and real addresses for the cache line from the cache directory allowing the directory to be small in size. Upon a memory access by a processing unit, a cache hash address is generated to access a translation lookaside buffer entry allowing comparison of the address stored in the TLB entry with the address of the memory access. Congruence implies a hit. Concurrently, the cache hash address indicates a pointer from the cache directory. The pointer should correspond to the cache hash address to indicate a cache directory hit. Where both occur a cache hit has occurred.

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