Compositions – Etching or brightening compositions
Reexamination Certificate
2001-08-23
2004-10-05
Goudreau, George A. (Department: 1763)
Compositions
Etching or brightening compositions
C252S079200, C252S079300, C252S079400
Reexamination Certificate
active
06800218
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to the chemical mechanical polishing of semiconductor devices systems and methods, and more particularly, to a formulation and method for use in polishing metal films in semiconductor interconnection processes.
BACKGROUND OF THE INVENTION
The present invention relates to a polishing formulation for surfaces of a semiconductor wafer, and more particularly, to a polishing formulation and a method for using the polishing formulation to remove and polish metal containing materials layered on semiconductor wafer surfaces.
Semiconductor wafers are used to form integrated circuits. The semiconductor wafer typically includes a substrate, such as silicon, upon which dielectric materials, barrier materials, and metal conductors and interconnects are layered. These different materials have insulating, conductive or semi-conductive properties. Integrated circuits are formed by patterning regions into the substrate and depositing thereon multiple layers of dielectric material, barrier material, and metals.
In order to meet the higher speeds required in large scale integration (LSI), semiconductor manufacturers are looking to copper and its alloys for interconnections due to its decreased resistivity. Copper is also less vulnerable to electromigration than aluminum and less likely to fracture under stress.
In conventional deposition, a layer of metal and a layer of a masking material called photoresist are deposited on a silicon wafer. Unwanted metal is then etched away with an appropriate chemical, leaving the desired pattern of wires or vias. Next, the spaces between the wires or vias are filled with silicon dioxide or other low k dielectric as insulator, and finally the entire wafer surface is polished to provide a planar surface and/or remove excess insulator. In copper deposition the damascene method is used wherein the pattern of wires or vias is first formed by etching the silicon dioxide or other suitable insulator such as fluorinated silica glass, Silk®, or methylsilsesquioxane etc. The metal is then deposited second.
Typically for copper technology, the layers that are removed and polished consist of a copper layer (about 1-1.5 &mgr;m thick) on top of a thin copper seed layer (about 0.05-0.15 &mgr;m thick). These copper layers are separated from the dielectric material surface by a layer of barrier material (about 50-300 Å thick).
In order to obtain the correct patterning, excess material used to form the layers on the substrate must be removed. Further, to obtain efficient circuits, it is important to have a flat or planar semiconductor wafer surface. Thus, it is necessary to polish certain surfaces of a semiconductor wafer.
Chemical Mechanical Polishing or Planarization (“CMP”) is a process in which material is removed from a surface of a semiconductor wafer, and the surface is polished (planarized) by coupling a physical process such as abrasion with a chemical process such as oxidation or chelation. In its most rudimentary form, CMP involves applying slurry, a solution of an abrasive and an active chemistry, to a polishing pad that buffs the surface of a semiconductor wafer to achieve the removal, planarization, and polishing process.
Copper CMP often employs a two-step slurry approach. The slurry used in the first step has a high copper removal rate and a comparatively low barrier material removal rate. The slurry used in the second step has a relatively high barrier material removal rate, comparable removal rate for copper and low or comparable removal rate on the dielectric material.
As successive layers are deposited across previously patterned layers of an integrated circuit, elevational disparity develops across the surface of each layer. If left unattended, the elevational disparities in each level of an integrated circuit can lead to various problems. For example, when dielectric, conductive, or semiconductive material is deposited over a topological surface having elevationally raised and recessed regions, step coverage problems may arise. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Also, stringers or fences may arise from incomplete etching, polishing, or redeposition of metal.
One key to obtaining good uniformity across the wafer surface is by using a polishing formulation that has a higher removal selectivity for copper than the underlying barrier layer. If such selectivity is not maintained, unwanted dishing of copper and/or erosion of the dielectric material may occur.
Typical commercial CMP slurries used to remove overfill material and polish semiconductor wafer surfaces have a barrier material removal rate below 500 Å/min. Further, these slurries have a copper to barrier material removal rate selectivity of greater than 4:1. This disparity in removal rates during the removal and polishing of the barrier material results in significant dishing of copper on the surface of the semiconductor wafer and/or poor removal of the barrier material.
Another problem with conventional CMP slurries is that the removal chemistry of the slurry is compositionally unstable. CMP slurries using ceria, alumina, or fumed silica must be continuously agitated or the abrasive particles will rapidly settle out. Further, many of the colloidal and fumed abrasives agglomerate after relatively short time frames following addition to the supporting chemistry. Both of these problems lead to significant operational obstacles such as the need for an expensive continuously recirculating distribution system equipped with filtration, chemistry monitoring, chemical addition equipment, and on-line particle monitors.
A further problem in commercial CMP slurries is that the abrasive materials in the slurries produce defects in the form of micro scratches. The scratches and other defects occur due to the solid abrasive, in particular alumina, which is the main material used as a metal polishing abrasive. Slurry remains behind in the micro-scratches causing the semiconductor device to fail. Micro scratches and poor planarization efficiency result in integrated circuits with increased defects and a lower yield.
Further, abrasive particles remain behind on the substrate surface after CMP. Cleaning machines or scrubbers using mechanical cleaning must be employed to remove the excess material.
Still another problem of commercial CMP slurries is that the chemicals that make up the slurries produce a copper surface that has a high corrosion tendency post polish.
A further problem that occurs in commercial CMP relates to the peeling of the metal film surface from the substrate due to frictional force between the polishing abrasive and the metal film surface.
A still further problem that exists for semiconductor manufacturers in commercial CMP is the cost of abrasives, polishing pads, slurry feeders, processor for slurry containing waste and stirrers to prevent sedimentation of the abrasive in the slurry feeder.
Further, since CMP machines are set up in cleanroom environments, the dust generated by the solid abrasive material must be kept to a minimum This requires expensive systems to be installed to suppress dust in the exhaust duct of the CMP machine;
Therefore, it is an object of this invention, to provide an abrasive free polishing formulation for the removal of copper and other metal interconnects that overcomes the current problems in CMP processing.
An object of this invention, therefore, is to provide an abrasive free polishing formulation having a high copper removal rate; high uniformity of the planarized surface and a comparatively low barrier material removal rate with minimal dishing and/or erosion.
These and other objects and advantages of the invention will be apparent to those skilled in the art upon reading the following detailed description and upon reference to the drawings.
SUMMARY OF THE INVENTION
The present invent
Baum Thomas H.
Bernhard David
Jones Michael
Ma Ying
Verma Deepak
Advanced Technology & Materials Inc.
Chappuis Margaret
Goudreau George A.
Hultquist Steven L.
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