Abnormal clock detector and abnormal clock detecting apparatus

Details Abnormal clock detector and abnormal clock detecting apparatus Abnormal clock detector and abnormal clock detecting apparatus

2000-11-03

2001-12-25

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By frequency

C327S040000

Reexamination Certificate

active

06333646

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an abnormal clock detector and an abnormal clock detecting apparatus for detecting a stop or an abnormal oscillation of a clock in an information processing apparatus.
BACKGROUND ART
An abnormal clock detector is disclose, f or example, in Japanese Patent Application Laid-open No. 4-306930. In this abnormal clock detector, as shown in
FIG. 16
, two different clocks (CK
1
and CK
2
) are compared with each other to detect which one of them is abnormal.
In the conventional abnormal clock detector shown in
FIG. 16
, since an abnormal clock is detected, the clocks CK
1
and CK
2
having different duty ratio or frequency are input a frequency divider
100
and a frequency divider
101
, respectively. Frequency of the input clocks CK
1
and CK
2
are respectively divided by frequency division ratios M
1
and M
2
in the frequency divider
100
and the frequency divider
101
. The clock CK
1
whose frequency was divided in the frequency divider
100
is output from the frequency divider
100
as a clock CK
4
having frequency f
4
. The clock CK
2
whose frequency was divided in the frequency divider
101
is output from the frequency divider
101
as a clock CK
3
having frequency f
3
. The clock CK
3
is input into a timing generator
102
. Here, the frequency division ratios M
1
and M
2
are arbitrary natural numbers satisfying a relation of 2·f
4
≧f
3
.
The clock CK
4
output from the frequency divider
100
are input into counters
103
and
104
, respectively, as input data. The clock CK
3
input into the timing generator
102
is output from the timing generator
102
as a reset pulse CK
5
, and the output reset pulse CK
5
is further input into the counters
103
and
104
, respectively, as reset pulses.
The counter
103
counts, during pulse interval of the reset pulse CK
5
, leading edges of the pulse of the clock CK
4
which is input data, and the counted pulse number S
up
is output. The counter
104
counts, during pulse interval of the reset pulse CK
5
, leading edges of the pulse of the clock CK
4
which is input data, and the counted pulse number S
down
is output.
The pulse numbers S
up
and S
down
respectively output from the counters
103
and
104
are input into an adder
105
. In the adder
105
, the pulse number S
up
is added to the pulse number S
down
, and the number of state change during pulse interval of the clock CK
4
of the reset pulse CK
5
, i.e., an addition value N
1
which is the number of pulse rising and falling edges of the pulse is output.
The addition value N
1
from output the adder
105
is input into a comparator
106
as input data B and to a comparator
107
as input data A. A reference value N
2
is further input into the comparator
107
as input data B, and the input data A is compared with the input data B to judge whether a relation A<B is satisfied. That is, the comparator
107
judges whether a relation of N
1
<N
2
is satisfied, and if the relation of N
1
<N
2
is satisfied, an error signal E
2
is output from the comparator
107
.
Here, the reference value N
2
is an arbitrary natural number satisfying a relation of N
2
·f
3
<2·f
4
≦(N
2
+1)·f
3
. N
2
+1 is input into the comparator
106
as input data A, and like the comparator
107
, the input data A is compared with the data B to judge whether a relation of A<B is satisfied. That is, the comparator
106
judges whether a relation of N
1
>N
2
+1 is satisfied. If the relation N
1
>N
2
+1 is satisfied, an error signal E
1
is output from the comparator
106
.
Since the pulse interval of the reset pulse CK
5
is determined by the frequency f
3
of the clock CK
3
, a relation of N
1
≦N
2
+1 is established with respect to the reference value N
2
satisfying the relation N
2
·f
3
≦2·f
4
<(N
2
+1)·f
3
in the clock CK
4
(frequency f
4
) and the reset pulse CK
5
(frequency f
3
) respectively input into the counters
103
and
104
. Therefore, when a relation N
1
>N
2
+1 is satisfied in the comparator
106
, this means that the frequency f
4
of the CK
4
is higher than its original frequency or the frequency f
3
of the CK
3
is lower than its original frequency, and an error signal E
1
is output from the comparator
106
.
If a relation N
1
<N
2
is satisfied in the comparator
107
, this means that the frequency f
4
of the CK
4
is lower than its original frequency or the frequency f
3
of the CK
3
is higher than its original frequency, and an error signals E
2
are output from the comparator
107
.
The error signals E
1
and E
2
respectively output from the comparators
106
and
107
are input into a judging device
108
together with a timing pulse TP output from the timing generator
102
, and an error flag EF indicative of abnormal clock CK
1
or CK
2
is output from the judging device
108
.
As explained above, according to the conventional abnormal clock detecting apparatus, frequencies of two different clocks to be detected are divided, the rising and falling edges of the clocks divided by the two counters are counted, the counted results are added by the adder, the addition result and the reference value are compared with each other by the comparator, thereby detecting the abnormal clock.
In the conventional abnormal clock detector, however, the adder, comparator for calculating the counted values by the counter, and the timing generator for generating the reset pulse and timing pulse are required, which complicates the circuit structure of the detector.
Especially in the case of the abnormal clock detector disclosed in Japanese Patent Application Laid-open No. 4-306930, it is not possible to specify one of two clocks to be detected, and this circuit structure can not detect abnormal condition of three or more clocks.
Therefore, it is an object of the present invention to provide an abnormal clock detector and an abnormal clock detecting apparatus capable of detecting abnormal condition of three or more different clocks with a simple circuit structure.
DISCLOSURE OF THE INVENTION
An abnormal clock detector of the present invention for detecting an abnormality of frequency of a first and second clock signals which are used as input signals, comprises: a first frequency divider circuit for dividing frequency of the first clock signal to output a first frequency division clock signal, a second frequency divider circuit for dividing frequency of the first clock signal to output a first reset signal, a third frequency divider circuit for dividing frequency of the second clock signal to output a second frequency division clock signal, a fourth frequency divider circuit for dividing frequency of the second clock signal to output a second reset signal, a first clock comparison circuit which inputs the first frequency division clock signal and the second reset signal, which counts the number of pulses of the first frequency division clock signal based on a state of the second reset signal, and which outputs a first error signal indicative of a clock abnormal state when the counted number of pulses exceeds a predetermined value; and a second clock comparison circuit which inputs the second frequency division clock signal and the first reset signal, which counts the number of pulses of the second frequency division clock signal based on a state of the first reset signal, and which outputs a second error signal indicative of a clock abnormal state when the counted number of pulses exceeds a predetermined value.
According to the present invention, it is possible to detect a higher state having frequency higher than original normal frequency, a lower state having frequency lower than original normal frequency and a stopped state of the two clocks to be detected only by the clock comparator and the frequency divider circuit without requiring complicated circuit as compared with the conventional abnormal clock detector.
A abnormal clock detector of the next invention, each of the first and second comparison circuits comprises an inverter gate for inverting a

Affiliated with

Also associated with

Rating

Abnormal clock detector and abnormal clock detecting apparatus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Abnormal clock detector and abnormal clock detecting apparatus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Abnormal clock detector and abnormal clock detecting apparatus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2601331