A field effect transistor logic gate having depletion mode and e

Details A field effect transistor logic gate having depletion mode and e A field effect transistor logic gate having depletion mode and e

1977-12-27

1979-12-04

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307213, 307215, 307270, 307304, H03K 1908, H03K 1912, H03K 1936, H03K 1940

Patent

active

041773900

ABSTRACT:
A logic gate having a first depletion mode field effect transistor with a gate electrode adapted for coupling to a control signal source, a second depletion mode field effect transistor and an enhancement mode field effect transistor, such enhancement mode field effect transistor being serially connected to the second depletion mode transistor. The second depletion mode transistor and the enhancement field effect transistor are fed by the first depletion mode transistor. One of such serially connected transistors has a Schottky gate contact. With such arrangement the logic gate includes a "complementary" pair of relatively short channel length devices fed by a relatively short channel length device to provide low static power dissipation and large output capacitance drive capability.

REFERENCES:
patent: 4028556 (1977-06-01), Cachier et al.
patent: 4101788 (1978-07-01), Baker
Nuzillat et al., "Subnanosecond Integrated Switching Circuit with MESFET's for LSI", IEEE-JSSC, vol-sc-11, No. 3, pp. 385-394, 6/1976.
Hayashi et al., "Design of ED-MOS Buffer", Electronics and Communications in Japan, vol. 55-c, No. 10, pp. 107-114, 10/1972.
Tuyl et al., "High-Speed Integrated Logic with GaAs MESFET's", IEEE-JSSC, vol. sc-9, No. 5, pp. 269-276, 10/1974.
Cahen et al., "A Subnanosecond Switching Circuit", Feb. 14, 1974 IEEE Int'l Solid-State Circuits Conf., pp. 110-111.

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