A data transfer control system for multiple units on a common bu

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Details

G06F 1516, G06F 104

Patent

active

044714254

DESCRIPTION:

BRIEF SUMMARY
This application arose upon entry into the national stage of prosecution of International Application, Ser. No. PCT/JP80/00137, filed June 19, 1980.


BACKGROUND OF THE INVENTION

This invention relates to a data-transfer controlling system, and more particularly to a system for transferring data between transmitter/receiver units connected to a common bus in which the number of conducting lines included in the common bus is reduced or the processing time for a transmitter/receiver unit to occupy the common bus is shortened.
In general, a data-transfer controlling system includes a plurality of transmitter/receiver units, such as processors, memory devices, input-output devices, etc, commonly connected to a common bus, and also includes a bus-control unit, which unit controls the signals of the transmitter/receiver unit requiring data transfer to be allowed or not allowed on the common bus. This control of allowing or not allowing the signals on the bus is usually executed during the time when a previous data transfer is effected between the transmitter/receiver units. In order to control the signals allowed on the common bus, the common bus in the prior art usually includes signal lines as follows:
However, for the purpose of simplifying the control and decreasing the cost of the common bus, it is desirable to reduce the number of signal lines in the common bus.
In addition, in the prior art system, the permission signal is transferred one after another through transmitter/receiver units connected in series, to a transmitter/receiver unit which has been providing a transfer-request signal. Therefore, due to the delay time of each transmitter/receiver unit, a relatively long time is required to reach the desired transmitter/receiver unit when a relatively large number of transmitter/receiver units are connected between the bus-control unit and the desired transmitter/receiver unit.


SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide a data-transfer controlling system in which the number of signal lines included in a common bus is reduced by allowing a permission-signal line to have the function of a busy-interlock signal line as well as the function of the permission-signal line itself.
Another object of the invention is to provide a data-transfer controlling system in which a desired transmitter/receiver unit which has been generating a transfer-request signal can be reached in a relatively short time.
According to the present invention, there is provided a data-transfer controlling system comprising a common bus including a plurality of conducting lines, a control unit connected to said common bus for controlling data transfer through said common bus, and a plurality of transmitter/receiver units for transferring data through said common bus to each other, said common bus including at least a transfer-request signal line connected to each of said transmitter/receiver units for conducting a transfer-request signal from a transmitter/receiver unit to said control unit, a permission-signal line for conducting a permission signal from said control unit to said transmitter/receiver unit which has been generating said transfer-request signal, for permitting said transmitter/receiver unit to transfer data, an acknowledge-signal line for conducting an acknowledge signal from a transmitter/receiver unit, which has received said permission signal, to said control unit, and a transfer-end signal line for conducting a transfer-end signal from a transmitter/receiver unit, to said control unit characterized in that: said control unit comprises a permission-signal generating means for generating said permission signal in response to the receiving of said transfer-request signal, wherein said permission signal is terminated in response to the generation of a transfer-end signal in the data-transfer process immediately before the current data-transfer process when said acknowledge signal has been generated before generating a transfer-end signal in said process immediately before sai

REFERENCES:
patent: Re31182 (1983-03-01), Crager et al.
patent: 3480914 (1969-11-01), Schlaeppi
patent: 3551892 (1970-12-01), Driscoll, Jr.
patent: 3959775 (1976-05-01), Valassis et al.
patent: 4040028 (1977-08-01), Tauker et al.
patent: 4099233 (1978-07-01), Barbagelata et al.
patent: 4151592 (1979-04-01), Suzuki et al.

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