A/D with digital PLL

Details A/D with digital PLL A/D with digital PLL

1998-11-17

2002-04-23

Butler, Dennis M. (Department: 2182)

Dynamic magnetic information storage or retrieval

Automatic control of a recorder mechanism

Controlling the head

C360S077050

Reexamination Certificate

active

06377416

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a semiconductor integrated circuit device and, more particularly, to a semiconductor integrated circuit device having a signal processor which processes signals read from a recording medium such as a magnetic disk. The signal processor includes a user data processing circuit having an A/D converter and a maximum likelihood decoder, and a servo data processing circuit which has an integrating circuit.
2. Description of the Related Art
There is a demand for a faster reading/writing speed for semiconductor integrated circuit devices, which process a digital signal associated with data read from a magnetic disk. Therefore, it is necessary to improve the operation speeds of a user data processing circuit and a servo data processing circuit which are used in such semiconductor integrated circuit devices.
A system for processing signals from a magnetic disk or other communication system decodes reception signals, using a maximum likelihood decoder, which performs maximum likelihood decoding, as one type of decoding means. In a communication system which transfers information in the form of a finite signal series, there are a plurality of transmission signal series which have probably been transmitted in association with one reception signal series. According to the maximum likelihood decoding, the reception side determines a transmission signal which is considered most appropriate based on some evaluation standards. A reception signal is associated with a transmission signal series in accordance with the decoding rules.
When a transmission signal which is not specified by the decoding rules is sent, a decoding error occurs. Given that Yi represents a reception signal series and X(Yi) represents a corresponding transmission signal series. When a transmission signal series X(Yi) has actually been transmitted and is received as a reception signal series Yi, no decoding error occurs. Given that the probability that such a event occurs is P(X(Yi), Yi), the probability P
E
that a decoding error occurs is expressed by the following equation:
P
E
=
∑
i
⁢
P
⁢
{
X
⁡
(
Yi
)
,
Yi
}
=
1
-
∑
i
⁢
{
X
⁡
(
Yi
)
}
⁢
P
⁢
{
Yi
|
X
⁡
(
Yi
)
}
Assuming that the probabilities of occurrence of transmission signal series are all the same, P(X(Yi)) becomes constant in any decoding rule. The minimum probability P
E
is therefore acquired by selecting X(Yi) which maximizes P(YiX(Yi)) with respect to Yi as a transmission signal series. Maximum likelihood decoding is carried out in this manner. A maximum likelihood decoder which executes this maximum likelihood decoding includes a plurality of metric arithmetic operation circuits. Each metric arithmetic operation circuit performs an operation on a transmission signal series X(Yi) and, based on the arithmetic operation result, selects transmission data corresponding to the transmission signal series X(Yi) from expected values of the transmission data written in a pass memory.
FIG. 1
is a block diagram showing a conventional maximum likelihood decoder. The maximum likelihood decoder has first to fourth metric arithmetic operation circuits
1
a
to
1
d
each having two inputs to respectively receive two digital signals A
1
and A
2
, B
1
and B
2
, C
1
and C
2
, or D
1
and D
2
. The first to fourth metric arithmetic operation circuits
1
a
-
1
d
perform addition or subtraction of the digital signal pairs A
1
and A
2
to D
1
and D
2
, and output first to fourth operation result values respectively. The maximum likelihood decoder further has a selector
2
and a fifth arithmetic operation circuit
1
e.
The selector
2
receives a first control signal CL
1
indicative of the value of the most significant bit (MSB) of the second operation result value, and a second control signal CL
2
indicative of the value of the MSB of the third operation result value. The selector
2
further selects one of the second to fourth operation result values in accordance with the first and second control signals CL
1
and CL
2
and outputs the selected operation result value to the fifth arithmetic operation circuit
1
e.
The fifth arithmetic operation circuit
1
e
has two inputs to respectively receive the first operation result value and one of the second to fourth operation result values. The fifth arithmetic operation circuit
1
e
performs addition or subtraction of the first operation result value and the operation result value selected by the selector
2
, and outputs a fifth operation result value.
However, it is difficult to improve the operation speed of a maximum likelihood decoder equipped with the above-described metric arithmetic operation circuits, for the following reason. The processing from the input of the digital signal pairs A
1
and A
2
through D
1
and D
2
, to the output of the operation result value from the fifth arithmetic operation circuit
1
e,
requires the arithmetic operation time and the selector operation time in two stages. After the first and second control signals CL
1
and CL
2
are produced based on the second and third operation result values, the selector
2
selects one of the second to fourth operation result values according to those control signals CL
1
and CL
2
. The fifth arithmetic operation circuit
1
e
then performs an operation on the first operation result value and one of the second to fourth operation result values.
If the operation speed of either the second or third arithmetic operation circuit
1
b
or
1
c
is slow, the time from the generation of the first and second control signals CL
1
and CL
2
to the supply thereof to the selector
2
is greater. This delays the selector operation and the arithmetic operation of the fifth arithmetic operation circuit
1
e.
Consequently, the operation speed of a maximum likelihood decoder having multistage metric arithmetic operation circuits becomes slower. This reduced operation speed affects the operation speed of the overall signal processing system which reads data from a magnetic disk and makes it difficult to improve the recording density of magnetic disks.
An operation test is conducted to check the product reliability of semiconductor integrated circuit devices, including maximum likelihood decoders such as that described above. The operation test for the maximum likelihood decoder supplies a serial signal from a testing device to a digital filter located at the preceding stage of the maximum likelihood decoder from a testing device. The maximum likelihood decoder receives the serial signal from the digital filter and decodes it. The testing device compares the decoded data with the serial signal to determine if the maximum likelihood decoder is operating properly.
In executing the operation test on a fast maximum likelihood decoder, the testing device should supply the serial signal at a high speed. That is, the testing device should also operate at a high speed. However, it is difficult to easily improve the operation speed of the testing device. In the operation test, generally, the internal circuit of a semiconductor integrated circuit device (LSI) operates in accordance with a scan clock signal supplied from the testing device, not a system clock signal. To date, however, the operation test of an LSI which operates in response to a system clock signal having a high frequency, cannot be conducted using a scan clock signal having a lower frequency than the system clock signal. In particular, for a fast LSI equipped with digital and analog circuits, as the ratio of the analog circuits to the digital circuits increases, a sufficient operation test cannot be accomplished with the slow testing device.
A signal processor which processes a read signal read from a magnetic disk includes a user data signal processing circuit, including the aforementioned maximum likelihood decoder, and a servo signal processing circuit. The user data signal processing circuit converts an analog signal, associated with user data included in the read signal, to a

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