Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-06-22
2001-10-16
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S136000, C341S156000, C341S162000, C341S158000, C341S118000, C341S120000, C341S110000, C341S155000, C341S163000
Reexamination Certificate
active
06304205
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The field of the present invention relates in general to analog-to-digital (A/D) conversion. More particularly the present invention relates to a multi-stage pipelined A/D converter.
2. Description of the Related Art
Analog-to-digital (A/D) converters are used in a wide variety of applications including telecommunications, radar, medical imaging, seismology, etc. There are numerous architectures for implementing A/D conversion including: flash, multi-step, pipeline, interplating, and time-interleaved successive approximation. The pipelined technique offers minimal circuit complexity, silicon area and power consumption with relatively high throughput.
In a pipelined architecture, the first stage operates on the most recent sample inputted while subsequent stages operate on residues from the prior samples output from prior stages of the cascaded pipeline architecture.
FIG. 1A
is a block diagram of a prior art pipelined A/D converter with three stages
110
,
120
,
130
. The converter includes a sample and hold unit
106
; first, second, and third stages respectively
110
,
120
,
130
; and a common clock
108
. Each stage makes a digital approximation of the amplitude of the analog sample presented to it and passes the amplified residue to the next stage where the process is repeated for the next most significant bits. In operation, an analog signal (e.g., channel
1
) on line
102
is delivered to a first sample and hold element
106
. The first stage makes the digital approximation of the most significant bits of the sampled signal and delivers that on bit line
112
. The amplified residue is presented on signal line
114
to the intermediate stage
120
. The intermediate stage generates a digital approximation of the most significant bits of the residue signal, which in this case corresponds to the intermediate significant bits of the sample obtained from channel
1
. These intermediate significant bits are output on bit line
122
and the amplified residue is output on signal line
124
. Signal line
124
provides the input to the final stage
130
which generates a digital signal corresponding to the most significant bits of the residue. These bits correspond with the least significant bits of the original sample of channel
1
. These are output on bit line
132
. The composite signal in serial or parallel form with a precision determined by the combined signals on bit lines
112
,
122
, and
132
is presented on digital signal line
104
. The common clock
108
drives each of the above-discussed components in a synchronous relationship. Each operates at the same clock speed.
As shown in
FIG. 1B
, each stage contains a sample and hold (SH)
158
, an A/D converter (ADC)
150
, a digital-to-analog converter (DAC)
156
, and a differencer
154
. The functions implemented by the DAC, SH and differencer may be implemented by a multiplying digital-to-analog converter (MDAC)
152
. Both the ADC
150
and the differencer
154
are coupled directly to the analog signal line
114
. The ADC
150
generates a signal corresponding the most significant bits of the signal received on signal line
114
. This signal is provided as an output on bit line
122
as well as an input to the DAC
156
. The DAC converts these most significant bits to analog form and provides them to the negative input of differencer
154
. The differencer outputs a residue signal corresponding to the difference between the input signal on line
114
and the most significant bits generated by ADC
150
on bit line
122
. The output of the summer is identified as a residue which is passed to the SH device
158
for output on signal line
124
. The SH device includes a gain element to amplify the residue.
The main advantage of pipelined ADCs are that they can provide high throughput rates and occupy small die areas. Both advantages stem from the concurrent operation of the stages; that is, at any time the first stage operates on the most recent sample, while all other stages operate on residues from previous samples. (The associated latency is not a limitation in many applications.) If the A/D are done with flash converters, pipelined architectures require only two main clock phases per conversion; therefore the maximum throughput rate can be high. Also, since the stages operate concurrently, the number of stages used to obtain a given resolution is not constrained by the required throughput rate. For multichannel applications, prior art pipelined A/D converters require proportionately larger die areas and have concurrently larger power dissipations.
What is needed is a A/D converter architecture with reduced die area and power dissipation for multichannel applications.
SUMMARY OF THE INVENTION
An apparatus and method for A/D conversion is provided. The apparatus provides for multi-path multi-channel (MPMC) pipelined A/D conversion. Unlike prior art designs in which the handling of multiple channels requires a linear increase in the associated circuitry and components, the current design scales for multiple channel A/D conversion with a less than linear increase in the number of components. This reduces the overall silicon area and power consumption of the apparatus as compared with prior art designs.
In an embodiment of the invention an A/D converter for obtaining digital samples from a plurality of analog information signals is disclosed. The A/D converter comprises a plurality of stages and interfaces between adjacent columns of the stages. The stages each include an input, a first output, and a second output. Each of the stages is responsive to an input signal applied to the input to output at the first output a bit signal corresponding to at least one significant bit of the input signal and to output at the second output a residue signal corresponding to a difference between the input signal and the bit signal. The stages are arranged in columns. The interfaces are located between adjacent columns for passing residue signals from an upstream one of the adjacent columns to the inputs of a downstream one of the adjacent columns. At least one interface includes a multiplexer. The multiplexer switchably couples residue signals from at least two of the puality of stages within the upstream one of the adjacent columns across one of the plurality of stages within the downstream one of the adjacent columns.
In an another embodiment of the invention, the A/D converter includes stages arranged as an upstream and a downstream column and a multiplexer. Each of the stages includes an input, a first output and a second output, and are responsive to an input signal applied to the input to output at the first output a bit signal corresponding to at least one significant bit of the input signal and to output at the second output a residue signal corresponding to a difference between the input signal and the bit signal. The multiplexer switchably couples residue signals from at least two of the stages within the upstream column across one of the stages within the downstream column.
In another embodiment of the invention, a method for obtaining digital samples from a plurality of analog information signals is disclosed. The method for converting comprises the acts of:
obtaining during a first time interval;
a) a first magnitude of a first of the plurality of analog information signals and a second magnitude of a second of the plurality of analog information signals; and
b) differencing the first magnitude with the first of the plurality of analog information signals to generate a first residue, and differencing the second magnitude with the second of the plurality of analog information signals to generate a second residue; and
obtaining during a second time interval beneath a selected threshold no greater than ½ the first time interval:
c) the magnitude of the first residue and the magnitude of the second residue; and
combining the first magnitude with the magnitude of the first residue to extend a precision of the first magnitude and combining the second magnitude with
Gunadisastra Peter
Rezvani Behrooz
Cary Charles C.
Cary & Kelly LLP
Ikanos Communications Inc.
Mai Lam T.
Tokar Michael
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