Coded data generation or conversion – Converter compensation
Reexamination Certificate
2000-03-24
2002-09-17
Phan, Trong (Department: 2818)
Coded data generation or conversion
Converter compensation
C341S120000, C341S155000
Reexamination Certificate
active
06452518
ABSTRACT:
This patent application claims priority based on Japanese patent applications, H11-080118 filed on Mar. 24, 1999 and 2000-54335 filed on Feb. 29, 2000, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device testing apparatus and in particular to an A-D converter and a calibration unit incorporated in the semiconductor device testing apparatus.
2. Description of the Related Art
FIG. 1
is a block diagram showing a typical A-D converter
101
, which converts an analog signal to a digital signal. The A-D converting apparatus
101
is comprised of an analog signal input portion
11
, A-D converters
13
a
and
13
b
, a sampling clock signal generator
15
, a reference clock signal generator
17
, a delay circuit
24
and an interleave processing unit
19
. The interleave processing unit
19
includes a multiplexer
29
and a memory unit
21
.
An analog signal
50
is input to the analog signal input portion
11
. The input analog signal
50
is sampled by the A-D converters
13
a
and
13
b
, which perform alternate sampling thereon, so as to be converted to a digital signal. The digital signals alternately output from the A-D converters
13
a
and
13
b
are put in a sequential order by the multiplexer
29
, so as to be stored in a memory unit
21
.
Based on a reference clock signal
54
, the sampling clock signal generator
15
generates sampling clock signals
56
a
and
56
b
which alternately trigger the sampling operation of the A-D converters
13
a
and
13
b
. A delay circuit
24
calibrates the timing of the sampling operation of the A-D converters
13
a
and
13
b
, and i is arranged on a transfer path of the sampling clock signals
56
a
and
56
b
generated from the sampling clock signal generator
15
.
FIG. 2
shows a readily available A-D converting apparatus
102
equipped with a plurality of analog signal portions. The A-D converting apparatus
102
includes A-D converters (
13
a
,
13
b
,
13
c
,
13
d
) corresponding to a plurality of analog signal input portions (
11
a
,
11
b
,
11
c
,
11
d
), respectively, a reference clock signal generator
17
and memory units (
21
a
,
21
b
,
21
c
,
21
d
).
Respective analog signals (
50
a
,
50
b
,
50
c
,
50
d
) are input to the respective analog signal input portions (
11
a
,
11
b
,
11
c
,
11
d
). The input analog signals are converted to digital signals by the respective A-D converters (
13
a
,
13
b
,
13
c
,
13
d
). The converted digital signals are stored in the memory units (
21
a
,
21
b
,
21
c
,
21
d
).
FIG. 3A
is a block diagram showing interleave processing. In interleave processing, sample data obtained from whichever of the two A-D converters
13
a
and
13
b
alternately sampling-operated, are put in sequential order by an interleave processing unit
19
. By performing the interleave operation, sample data equivalent to a higher sampling rate than that of a single A-D converter is obtained. Referring to
FIG. 3B
, in interleave processing, the two A-D converters
13
a
and
13
b
are alternately triggered to sampling-operate, by supplying to the A-D converters two sampling clock signals
56
a
and
56
b
, whose respective phases are displaced from each other.
As mentioned above, interleave processing is a method by which digital signals output from a plurality of A-D converters are put in sequential order. In interleave processing, sampling sampling-operates, based on the sampling clock signal. However, in actuality, a time error occurs against a desired sampling clock, due to characteristic differences between respective A-D converters and those between the transfer paths of the sampling clock signal. Thus, calibration of the time error is necessary. As shown in
FIG. 1
, in the conventional practice, the time error is calibrated by providing a variable delay element in the midst of the path leading the sampling clock signals
56
a
and
56
b
to the respective A-D converters.
The conventional A-D converting apparatus
101
shown in
FIG. 1
performs only the interleave process by which the A-D converters
13
a
and
13
b
are alternately sampling-operated. The A-D converting apparatus
101
cannot perform other processes.
In the conventional A-D converter
102
shown in
FIG. 2
, the A-D converter to be used for processing the analog signal input from each analog signal input portion is fixed in advance. Moreover, the delay circuit carries out calibration of the time error, making the calibration of the time error very complicated. Furthermore, the range in which the time error can be calibrated heavily depends on the performance of the delay circuit, so that high precision calibration cannot be performed.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide an A-D converting apparatus, a calibration unit and a semiconductor device testing apparatus and methods therefor to aid in solving at least one of the above disadvantages. These objects will be achieved by combining features described in the independent claims in the scope claims. Moreover, dependent claims provide further advantageous embodiments according to the present invention.
According to one aspect of the present invention, there is provided analog-to-digital (A-D) converting apparatus which samples an analog signal output from a semiconductor device under test to produce a digital signal, comprising: an analog signal input portion which inputs the analog signal; a plurality of analog-to-digital (A-D) converters which samples the analog signal input at said analog signal input portion, and convert the analog signal to the digital signal; a sampling clock signal generator which supplies either a synchronous sampling clock signal for use with an averaging process so as to sampling-operate the plurality of A-D converters in a synchronized manner, or an alternate sampling clock signal for use with an interleave process so as to alternately sampling-operate the plurality of A-D converters; an averaging processing unit which performs the averaging process on the digital signal output from the sampling-operated A-D converters, based on the synchronous sampling clock signal; and an interleave processing unit which interleaves the digital signal output from the sampling operated A-D converters, based on the alternate sampling clock signal.
The A-D converting apparatus may further comprise a mode specifying signal generator which generates a mode specifying signal which specifies either the averaging process or the interleave process, whereby either the averaging process unit or the interleave processing unit is selected based on the mode specifying signal.
Moreover, the A-D converting apparatus may further comprise a reference clock signal generator which generates a reference clock signal, wherein the sampling clock signal generator supplies the synchronous sampling clock signals synchronized with the reference clock signal to the respective A-D converters in the event that the averaging process is specified by the mode specifying signal while said sampling clock signal generator supplies the alternate sampling clock signal each having a different phase from other to said respective A-D converters in the event that the interleave process is specified by the mode specifying signal.
Moreover, the A-D converting apparatus may further comprise a plurality of memory units which store the digital signals output from the respective plurality of A-D converters, wherein the averaging processing unit and the interleave processing unit perform the averaging process and the interleave process, respectively, based on the digital signal stored in the plurality of memory units.
Suppose that there are a first A-D converter and a second A-D converter, the A-D converting apparatus may further comprise: an error calculation unit which calculates a time error which is a time displacement between a predetermined timing sampled by the second A-D converter against that sampled by the first A-D converter and an actua
Advantest Corporation
Phan Trong
Rosenthal & Osha L.L.P.
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