Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1999-10-15
2001-09-11
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S156000
Reexamination Certificate
active
06288661
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention pertains in general to analog-to-digital converters and, more particularly, to a successive approximation register A\D converter utilizing a combination of a resistive DAC and a capacitive DAC.
BACKGROUND OF THE INVENTION
High-resolution successive-approximation analog-to-digital (A\D) converters suffer from the disadvantage that they require in-depth ratio-accurate circuit elements to achieve N-bit monotonic conversion, even if N-bit absolute accuracy is not required. As the number of bits, N, increases, the matching requirement on the circuit elements becomes tighter. One method to achieve tighter matching requirements in a monolithic integrated circuit is to increase the dimensions of the precision-ratioed elements in order to reduce the mismatch due to random edge variation caused during processing. This alternative, however, reduces the processing yield. A second alternative is to utilize on-chip trimming techniques.
In general, the A\D converter is made up of a digital-to-analog converter section (DAC) and a comparator. The DAC portion is the portion that requires tight matching of the selectable elements. In the capacitor DACs, various capacitors are utilized which are switched in and out of the circuit to provide the discrete steps. However, this can lead to non-monotonic behavior due to the mismatch between the capacitors. This situation is exacerbated as the resolution of the DAC increases. Monotonicity can be resolved by utilizing a resistor DAC which utilizes a resistor string. These are inherently monotonic.
Monotonic behavior is necessary for any control-system application. Although the resistor DAC will exhibit inherently monotonic behavior, it can become very large when implementing resolutions beyond the eight-bit level. For example, a nine-bit resistor DAC is roughly twice the size of an eight-bit resistor DAC. A ten-bit resistor DAC is roughly four times the size of an eight-bit resistor DAC. Moreover, a resistor DAC is most accurately implemented when the resistors are physically laid out in a linear fashion-one straight long resistor from end to end. As the resistor DAC resolution increases, this long resistor string can span one dimension of the chip and perhaps even push one dimension beyond this limit in order to accommodate the length of the resistor. Adding bends or serpentine sections to improve area use only increases the differential non-linearity (DNL) of the A/D converter performance. DNL performance of resistor DACs is very good due to the fact that DNL depends upon matching of adjacent unit components such that there are no major transitions where DNL is the most sensitive. The non-linearity performance of the resistor DACs is limited by the matching across the entire length of the string.
One type of resistor DAC that utilizes a smaller number of resistors to gain higher resolutions is that described in B. Fotouhi and D. H. Hodges, “High-Resolution A\D Conversion in MOS\LSI,” IEEE J. Solid-State Circuits, vol. SC 14, pp. 920-926, Dec. 1979, which is incorporated herein by reference. Fotouhi discloses a successive approximation register DAC utilizing a resistor string combined with a binary weighted capacitor string. It employs an M-bit resistor string with a K-bit binary ratioed capacitor array to achieve N equal M+K conversion. The resistor string provides an inherently monotonic division of the referenced voltage into 2
M
nominally identical voltage segments. The binary weighted-capacitor array is then used to subdivide any one of the segment voltages derived from the resistor string into 2
K
levels. One disadvantage to this system is that the first division provided by the resistor string, although being inherently monotonic, does not carry over into the switching of the capacitors, since they lack the monotonicity of the resistor string.
SUMMARY OF THE INVENTION
The present invention disclosed and claimed herein comprises an analog-to-digital converter having a digital-to-analog converter section for converting a Z-bit digital word. The digital-to-analog converter section includes an MSB portion for receiving a predetermined portion of the upper most significant bits, M bits, of the digital word and providing a monotonic division, V
INC
, of a reference voltage to provide a first analog voltage. A SubDAC portion is provided for receiving the remaining portion of the digital word, N bits, and providing a monotonic division of the voltage V
INC
to provide a second analog voltage. A summing device sums the first analog voltage with the second analog voltage to provide an analog output voltage with an M+N bit resolution, Z=M+N.
REFERENCES:
patent: 4338591 (1982-07-01), Tuthill
patent: 4749984 (1988-06-01), Prost et al.
patent: 5220483 (1993-06-01), Scott
patent: 5343199 (1994-08-01), Sugawa
patent: 5581252 (1996-12-01), Thomas
patent: 5617091 (1997-04-01), Uda
patent: 5627537 (1997-05-01), Quinlan et al.
patent: 5703588 (1997-12-01), Rivoir et al.
patent: 5731775 (1998-03-01), Gross, Jr. et al.
patent: 6137430 (2000-10-01), Lyden et al.
A Monolithic Charge-Balancing Successive Approximation A/D Technique, Thomas P. Redfern, Joseph J. Connolly, Jr., Sing W. Chin and Thomas M. Frederiksen,IEEE J. Solid State Circuits, vol SC-14, pp. 912-920, Dec. 1979.
“High Resolution A/D Conversion in MOS/LSI”; Bahram Fotouhi and David A. Hodges;IEEE J. Solid State Circuits, vol SC-14, pp. 920-926, Dec. 1979.
“Technological Design Considerations for Monolithic MOS Switched-Capacitor Filtering Systems”, David J. Allstot and William C. Black, Jr.,Proc.IEEE, vol. 71, pp. 967-968, Aug. 1983.
“Error Correction Techniques for High-Performance Differential A/D Converters”, Khen-Sang Tan, Sami Kiriaki, Michiel De Wit, John W. Fattaruso, Ching-Yuh Tsay, W. Edward Matthews and Richard K. Hester;IEEE J. Solid State Circuits, vol. 25, No. 6, Dec. 1990.
“A 12-b 5-MSample/s Two-Step CMOS A/D Converter”, Behzad Razavi and Bruce A. Wooley,IEEE J. Solid State Circuits, vol. 27, No. 12, Dec. 1992.
“An IEEE 1451 Standard Transducer Interface Chip with 12-b ADC, Two 12-b DAC's, 10-kB Flash EEPROM, and 8-b Microcontroller”, Tim Cummins, Eamonn Byrne, Dara Brannick and Dennis A. Dempsey,IEEE J. Solid State Circuits, vol. 33, No. 12, Dec. 1998.
Cygnal Integrated Products, Inc.
Howison, Chauza, Thoma, Handley & Arnott LLP
Wamsley Patrick
LandOfFree
A/D converter with voltage/charge scaling does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with A/D converter with voltage/charge scaling, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and A/D converter with voltage/charge scaling will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2523125