A/D converter with prevention of comparator output discontinuiti

Details A/D converter with prevention of comparator output discontinuiti A/D converter with prevention of comparator output discontinuiti

1988-11-01

1990-04-17

Shoop, Jr., William M.

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341155, H03M 100

Patent

active

049184512

ABSTRACT:
A reference voltage is divided by a plurality of resistors (6), the respective voltages and an analogue input voltage being compared with each other by comparators (7). An output of each of the comparators is applied to a data transfer circuit (13) of a hand shake type and latched. The data transfer circuit shifts discontinuous portions of logic which appeared in latched data. Therefore, simultaneous selection of a plurality of addresses in an encoder (10) is avoided.

REFERENCES:
patent: 4276543 (1981-06-01), Miller et al.
patent: 4644322 (1987-02-01), Fujita
patent: 4752766 (1988-06-01), Shimizu et al.
patent: 4768016 (1988-08-01), Chu et al.
"Transfer System of Data Driving Type Processor Q-p", (National Conference on the 32nd Jyohosyorigakkai; Society of Information Processing (First Term, 1986).
A. Dingwall, "Monolithic Expandable 6 bit 20 MHz CMOS/SOS A/D Converter", IEEE Journal of Solid-State Circuits, vol. SC-14, No. 6 (Dec. 1979).

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