Coded data generation or conversion – Converter compensation
Reexamination Certificate
2002-10-22
2004-06-01
Williams, Howard L. (Department: 2819)
Coded data generation or conversion
Converter compensation
C341S143000, C073S861010, C702S086000
Reexamination Certificate
active
06744389
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority of Swiss patent application 0220/00, filed Feb. 4, 2000, the disclosure of which is incorporated herein by reference in its entirety.
BACKGROUND
The invention relates to an A/D-converter.
The invention relates to and A/D-converter according to the preamble of the independent claims.
For handling and processing measured values it is often necessary to combine several input signals with each other for obtaining a desired output signal. For example, pressure and flow sensors are usually dependent on temperature such that their signal has to be corrected in view of the present temperature. This is usually carried out in digital computing units.
For this purpose, all measured signals are usually first digitized and then combined using calculations or by means of a table. However, if they are combined by means of a calculation, multiplications and divisions have to be carried out, which is only possible in complicated circuits. Similarly, tables, if used, become also very large for high resolution. For reducing the table size, interpolation between table values can be used, but this again requires multiplications or divisions.
SUMMARY OF THE INVENTION
Hence, it is an object of the invention to provide an A/D-converter of the type mentioned above that is able to combine two or more analog input values and to generate an output value of high precision while the required circuitry remains as small as possible.
This object is met by the A/D-converter according to the invention.
This object is met by the A/D-converter according to claim 1.
Hence, according to the invention a converter generating a digital value is attributed to each input. The digital values of all converters are fed together to a table and are converted to a lookup value. Several consecutive lookup values are then filtered in a decimation filter, e.g. by adding or averaging, in order to generate an output value that has higher resolution than the lookup value. This architecture allows to use a converter of comparatively low resolution, which reduces the size of the table and allows to keep the whole circuit small because the combination of the two or more input signals is also carried out at low resolution. Only by the addition or averaging or filtering after the table the desired resolution is reached.
The table is preferably organized as a memory, but it can also be implemented as an arithmetic unit.
As the table will usually generate a non-linearity between input and output signal, offset compensation of the circuit is preferably implemented by correcting the digital values with a correction value between the converters and the table.
In a further aspect, the invention has the object to provide an A/D-converter of the type mentioned above that has one or two inputs and that allows an efficient offset correction.
In a further aspect, the invention has the object to provide an A/D-converter of the type mentioned above that has one or two inputs and that allows an efficient offset correction. This object is also achieved by the independent claims.
For this purpose, the digital values between the converter and the table are also corrected by a correction value. The correction value can be determined by applying a known analog input value (preferably 0 volt) to the corresponding converter—and, where applicable, a analog stage arranged before the converter, which analog stage is considered to be part of the converter—and the offset of the corresponding digital value is compared to its expected value. For increasing the resolution of the correction, the offsets of n digital values are added for generating a correction word k. The value of k
rounded to the next lower integer, i.e. the value k div n, is then used for offset compensation of each digital value. To further increase resolution, the value k mod n, i.e. the remainder of the division, can be added for the correction of a group of n digital values to be corrected, by correcting part of the digital values of the group. Preferably, k mod n digital values of the group are corrected by a value of 1. In order to simplify this mathematical operations, n is preferably an integer power of 2.
The following embodiments relate to both aspects of the invention.
Preferably, circuits having a digitizer that converts the input value to a series of binary values are used as converters, wherein the number of the binary values with value 1 is proportional to the input value. By counting the binary values during a measuring period, the desired digital value can be generated. Examples for such converters are incremental converters or &Sgr;&Dgr;-converters.
When using such converters, the table can generate difference values that are accessed upon each increment of a counter and added to the value of an integrator stage used as decimation filter. Preferably, a proportionality constant is added at the same time such that the table only needs to store the deviations in respect to a corresponding linear interpolation, which further reduces memory requirements.
In order to reduce the number of accesses to the table, the table can be driven using a cache circuit having an intermediate storage for a part of the generated address values and the corresponding lookup values and returns these, when possible, without using the table. This allows to reduce the power consumption and/or electric noise generated by the circuit.
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Haeberli Andreas Martin
Mayer-Friedrich Felix Martin
Rothacher Urs Martin
Cooper & Dunham LLP
Dowden Donald S.
Sensirion AG
Williams Howard L.
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