Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-11-14
2002-11-12
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S159000, C341S161000, C341S160000, C341S162000, C341S172000, C341S122000
Reexamination Certificate
active
06480132
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2001-67049, filed on Mar. 9, 2001, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an A/D converter for converting an input analog signal into a digital signal.
2. Description of the Related Art
With the rapid progress of digital signal processing technologies in recent years, sophistication is increasingly demanded of A/D converters which are the interfaces with analog circuits. Among high-speed, low-power configurations of A/D converters is an interpolation type two-stage serial parallel scheme.
FIG. 18
shows the configuration of a two-stage serial parallel type A/D converter described in Japanese Patent Laid-Open Publication No.Hei 3-157020. This A/D converter is a two-stage serial parallel type A/D converter which utilizes interpolation to perform A/D conversion in two stages consisting of an upper A/D conversion block 1831 and a lower A/D conversion block 1832.
The A/D converter comprises a reference voltage generating circuit
1801
composed of a series of resistors, a differential amplifier row
1802
, a sample/hold (S/H) circuit row
1803
, comparator rows
1804
and
1812
, a switch row
1805
, an upper encoder
1806
, S/H circuits
1807
and
1808
, differential amplifiers
1809
and
1810
, a resistive interpolation circuit
1811
, and a lower encoder
1813
.
Initially, in the upper A/D conversion block
1831
, the differential voltages between individual reference voltages obtained from the reference voltage generating circuit
1801
and an analog input voltage are amplified by the differential amplifier row
1802
. The differential voltages are sampled/held by the S/H circuit row
1803
. The differential voltages held by the S/H circuit row
1803
are compared in the comparator row
1804
. The outputs of the comparator row
1804
are converted into binary digital code by the upper encoder
1806
, obtaining an upper A/D conversion result
1821
.
At the same time, the upper encoder
1806
generates a control signal CTL for turning on certain switches in the switch row
1805
, so that differential voltages with two reference voltages in the vicinity of the input voltage, out of the differential voltages held by the S/H circuit row
1803
are transferred to the lower A/D conversion block
1832
. The two differential voltages transferred are sampled/held by the S/H circuits
1807
and
1808
. The noninverted outputs and inverted outputs of the differential amplifiers
1809
and
1810
are individually interpolated by the resistive interpolation circuit
1811
. The resulting interpolated voltages are compared in the comparator row
1812
. The lower encoder
1813
converts the outputs of the comparator row
1812
into binary digital code to obtain a lower A/D conversion result
1822
.
Hereinafter, description will be given in conjunction with an operation timing chart of
FIG. 19. A
signal
1901
is a signal of the S/H circuit row
1803
. A signal
1902
is a signal of the comparator row
1804
. A signal
1903
is a signal of the selector switch
1805
. A signal
1904
is a signal of the S/H circuits
1807
and
1808
. A signal
1905
is a signal of the comparator row
1812
. The signals
1901
and
1902
are signals
1911
of the upper A/D conversion block
1831
. The signals
1904
and
1905
are signals
1912
of the lower A/D conversion block
1832
. A conversion cycle
1921
of the A/D converter is the sum of period a
1
, b
1
, and c
1
.
The S/H circuit row
1803
, after a sample mode in the period a
1
, changes from the sample mode to a hold mode. The held voltage is settled in the period b
1
. The comparator row
1804
starts its comparing operation in the period b
1
, and outputs the result in the period c
1
. At the same time, the encoder
1806
generates the upper A/D conversion result
1821
and a control signal CTL from the comparison outputs, and keeps certain switches
1805
on over the period c
1
. During the period c
1
in which differential voltages are transferred from the upper A/D conversion block
1831
to the lower A/D conversion block
1832
, the S/H circuits
1807
and
1808
are in a sample mode. The S/H circuits
1807
and
1808
change to a hold mode in the period a
2
.
On the other hand, at the period a
2
, the S/H circuit row
1803
returns to the sample mode. In the lower A/D conversion block
1832
, the outputs of the interpolation circuit
1811
are settled in the period a
2
before the comparator row
1812
starts its comparing operation. From the comparisons, the encoder
1813
outputs the lower A/D conversion result
1822
at the period b
2
. It is the operating speed of the S/H circuit row
1803
that determines the conversion speed (sampling frequency) of the A/D converter. Thus, as shown in
FIG. 19
, the sum of the periods a
1
, b
1
, and c
1
fixes the conversion cycle of this A/D converter.
In the interpolation type two-stage serial parallel scheme, the following three points are important, in terms of operating timing, to prevent a deterioration in conversion accuracy:
(1) Start the comparing operation of the comparator rows
1804
only after the S/H circuit row
1803
is sufficiently settled and stabilized in hold voltage.
(2) Secure longer time (period c
1
) for transferring differential voltages from the upper A/D conversion block
1831
to the lower A/D conversion block
1832
so that the S/H circuits
1807
and
1808
can well follow in sampling operation.
(3) Set the timing to turn off the switches
1805
for transferring differential voltages from the upper A/D conversion block
1831
to the lower A/D conversion block
1832
in advance of switching the S/H circuit row
1803
from the hold mode to the sample mode.
The interpolation type two-stage serial parallel scheme shown in
FIG. 18
has the following problems. A rise in the number of bits to be converted in the lower stage increases the number of interpolation nodes by power of 2. In each interpolation node, the settling time of the interpolation voltage is determined by the time constant between the load capacitance and the interpolation resistance of that interpolation node. The greater the number of bits to be converted in the lower stage, the slower the operating speed of the interpolation circuit becomes. At higher conversion speeds, the interpolating operations therefore fail to follow the changes of the differential voltages transferred from the upper A/D conversion block, deteriorating the conversion accuracy in the lower stage.
From the foregoing it will be seen that when a high-speed high-resolution A/D converter is to be configured as shown in
FIG. 18
, the number of bits to be converted at the lower stage is appropriately set to a smaller value (no greater than 3 bits) so as to suppress an interpolation-originated deterioration in conversion accuracy. Nevertheless, due to its two-stage configuration consisting of upper and lower stages, the serial parallel type ends up requiring a greater number of bits in upper stage A/D conversion, to constitute a high-resolution A/D converter. This spoils the advantages of the serial parallel type over a full flash type, such as smaller parts numbers and a reduction in power consumption.
The S/H circuit row
1803
must remain in the hold mode until differential voltages are transferred to the lower A/D conversion block completely. This fixes the conversion speed of the A/D converter as shown in FIG.
19
.
On the other hand, the comparator row
1804
starts comparisons in the period b
1
. This comparison start timing is preferably set as close to the end of period b
1
as possible, considering the sufficient settling of the hold voltages in the S/H circuit row
1803
. In reality, however, the encoder
1806
inevitably has a circuit-operation delay time before generating the control signal CTL for the switches
1805
out of the comparison outputs of the comparator row
1804
. Therefore, if the comparison start t
Tsukamoto Sanroku
Yoshioka Masato
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Mai Lam T
Tokar Michael
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