A/D converter with adaptive background calibration skip rate

Details A/D converter with adaptive background calibration skip rate A/D converter with adaptive background calibration skip rate

2003-02-25

2004-08-31

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S156000, C341S155000, C341S118000

Reexamination Certificate

active

06784815

ABSTRACT:

TECHNICAL FIELD
The present invention relates to analog-to-digital (A/D) converters, and in particular to background calibration of such converters.
BACKGROUND
The performance of any A/D converter is limited by non-ideal effects associated with its various building blocks. The influence of several such effects can be addressed by digital calibration, e.g. as described in [1], where a set of digital calibration coefficients are used to correct the estimated analog circuit errors. A problem is that the calibration coefficients are most accurate when the circuit is operated under exactly the same conditions as when the coefficients were estimated. If, for example, the temperature, the supply voltage, or a bias current is changed, a new set of coefficients may be required for optimal error correction.
Usually, a technique called background calibration [2] is used to continuously calibrate the A/D converter during normal operation. However, the background calibration process disturbs the normal signal flow through the A/D converter, and therefore causes an error in the output. There are techniques to reduce the magnitude of such errors, e.g. by interpolation as described in [3]. During a background calibration sequence this “skip-and-fill” method creates time slots for calibration by interrupting sampling for every k
th
sample position and inserting an interpolated sample into the output stream. Such calibration sequences are continuously repeated. Nevertheless, the interpolated samples produced by the background calibration of the A/D converter lead to an increased bit-error rate in, for example, digital communication systems. It would be desirable, both from a signal quality and power efficiency point of view, to suppress background calibration of the A/D converter as much as possible.
SUMMARY
An object of the present invention is to provide background calibration techniques for A/D converters at a lower bit-error rate penalty than in the prior art.
This object is achieved in accordance with the attached claims.
Briefly, the present invention is based on the insight that background calibration is normally not necessary during times when operating conditions are stable. By using on-chip or off-chip sensors for critical operating parameters, such as temperature and supply voltage, it becomes possible to track changing operating conditions and to decrease the sample skip rate of the background calibration under stable conditions, thus lowering the bit-error rate in steady-state. A further advantage of this approach is that tracking of operating conditions also gives the possibility of increasing the skip rate if these conditions are changing very rapidly. In this situation it may be better to slightly increase the error level caused by background calibration in order to obtain a constantly calibrated converter.


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