A/D converter preventing results of A/D conversion from...

Details A/D converter preventing results of A/D conversion from... A/D converter preventing results of A/D conversion from...

2008-06-02

2009-11-10

Mai, Lam T (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Multiplex

C341S155000

Reexamination Certificate

active

07616140

ABSTRACT:
An A/D converter capable of generating an interrupt for requesting a control circuit to read the results of A/D conversion, in desired timing. Analog signals input from channels selected by a channel-selecting section are input to an A/D conversion section, and are sequentially A/D-converted. The results of A/D conversion are sequentially stored in different stages of a FIFO. A stage number-counting section counts the number of the stages of the FIFO where the results of A/D conversion are stored. An interrupt signal-delivering section outputs an interrupt signal for requesting a CPU to read the results of A/D conversion when the number of stages counted by the stage number-counting section is equal to an interrupt-generating stage number set by an interrupt-generating stage number-setting section.

REFERENCES:
patent: 5812928 (1998-09-01), Watson et al.
Patent Abstracts of Japan: Japanese Patent Publication No. 09-269870, Publication Date: Oct. 14, 1997, Inventor: Oya Mitsunari. (1 page only).

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