A/D converter for performing pipeline processing

Details A/D converter for performing pipeline processing A/D converter for performing pipeline processing

2002-09-27

2004-03-02

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000, C341S120000

Reexamination Certificate

active

06700524

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to an A/D converter and, more particularly, to an A/D converter performing pipeline processing, which can vary resolution.
BACKGROUND OF THE INVENTION
With digitization and speedup of signal processing in information communication fields as well as downsizing and weight-reduction of information communication devices, speedup and reduction in power consumption are required of A/D converters which become key devices in digital signal processing. In recent years, a pipeline A/D converter has increasingly been employed as a configuration of an A/D converter to meet the requirements. First of all, the construction and operation of a conventional pipeline A/D converter will be described.
FIG. 17
is a block diagram illustrating a general pipeline A/D converter of 5-bit output, using three pipeline stages of 1.5-bit output, and a final pipeline stage of 2-bit output (refer to Japanese Published Patent Application No. Hei.6-85672, Japanese Published Patent Application No. Hei.10-173528, and “CMOS DATA CONVERTERS FOR COMMUNICATIONS” by Mikael Gustavsson, J. Jacob Wikner, Nianxiong Nick Tan, KLUWER ACADEMIC PUBLISHERS (ISBN-0-7923-7780-X)).
The pipeline A/D converter is supplied with an analog input signal
1
as an input, and outputs a digital output signal
2
. The analog input signal
1
indicated by a partial analog voltage value P
0
is connected to a first pipeline stage
3
. An output of the first pipeline stage
3
, which is indicated by a partial analog voltage value P
1
, is connected to a second pipeline stage
4
. An output of the second pipeline stage
4
, which is indicated by a partial analog voltage value P
2
, is connected to a third pipeline stage
5
. An output of the third pipeline stage
5
, which is indicated by a partial analog voltage value P
3
, is connected to a fourth pipeline stage
6
. On the other hand, partial digital values M
1
L
1
-M
4
L
4
obtained in the respective pipeline stages are connected to a coding circuit
7
. There is a case where the analog input signal
1
is connected to the first pipeline stage
3
via a sampling/hold circuit (not shown). The foregoing is the construction of the pipeline A/D converter.
Next, a description will be given of the operation of the pipeline A/D converter for converting the analog voltage values into the digital values. When the analog input signal
1
indicated by the partial analog voltage value P
0
is input to the first pipeline stage
3
, the first pipeline stage
3
outputs the partial digital value M
1
L
1
which is a binary code having 1.5 bits of information and constitutes a most significant bit of the digital output signal
2
, and the partial analog voltage value P
1
, according to the analog input signal
1
. The partial digital value M
1
L
1
and the partial analog voltage value P
1
are input to the coding circuit
7
and the second pipeline stage
4
, respectively.
Likewise, when the partial analog voltage value P
1
is input to the second pipeline stage
4
, the second pipeline stage
4
outputs the partial digital value M
2
L
2
which is a binary code having 1.5 bits of information, and the partial analog voltage value P
2
, according to the partial analog voltage value P
1
. The partial digital value M
2
L
2
and the partial analog voltage value P
2
are input to the coding circuit
7
and the third pipeline stage
5
, respectively. Likewise, when the partial analog voltage value P
2
is input to the third pipeline stage
5
, the third pipeline stage
5
outputs the partial digital value M
3
L
3
which is a binary code having 1.5 bits of information, and the partial analog voltage value P
3
, according to the partial analog voltage value P
2
. The partial digital value M
3
L
3
and the partial analog voltage value P
3
are input to the coding circuit
7
and the third pipeline stage
6
, respectively. Further, when the partial analog voltage value P
3
is input to the fourth pipeline stage
6
, the fourth pipeline stage
6
outputs the partial digital value M
4
L
4
which is a binary code having 2 bits of information and constitutes a least significant bit, according to the partial analog voltage value P
3
. The partial digital value M
4
L
4
is input to the coding circuit
7
.
The partial digital value L
1
and the partial digital value M
2
, the partial digital value L
2
and the partial digital value M
3
, and the partial digital value L
3
and the partial digital value M
4
have overlap portions (0.5 bit), respectively, to increase reliability in the conversion process, and the digital output signal
2
which is a binary code and has 5-bit resolution is consequently outputted by coding these digital values in the coding circuit
7
. The foregoing is the operation of the pipeline A/D converter.
Next, a description will be given of the constructions and operations of the general pipeline stages constituting the conventional pipeline A/D converter.
Hereinafter, the constructions of the i-th (first to fourth) pipeline stages will be described.
FIG. 18
is a block diagram illustrating the specific construction of each of the first to third pipeline stages
3
-
5
shown in FIG.
17
. Each of the first to third pipeline stages
3
-
5
is supplied with, as an input, a first partial analog voltage value
8
indicated by Pi−1, and outputs a partial digital value
9
indicated by MiLi, and a second partial analog voltage value
10
indicated by Pi. The first partial analog voltage value
8
is connected to a first offset addition unit
11
, an output of the first offset addition unit
11
is connected to a partial A/D converter
12
, an output of the partial A/D converter
12
is connected to a partial D/A converter
13
, an output of the partial D/A converter
13
is connected to a second offset addition unit
14
, an output of the second offset addition unit
14
and the first partial analog voltage value
8
are connected to a subtracter
15
, an output of the subtracter
15
is connected to an arithmetic amplifier
16
, an output of the arithmetic amplifier
16
becomes the second partial analog voltage value
10
, and an output of the partial A/D converter
12
becomes the partial digital value
9
.
On the other hand,
FIG. 19
is a block diagram illustrating the specific construction of the fourth pipeline stage
6
shown in FIG.
17
. The fourth pipeline stage
6
is supplied with, as an input, a first partial analog voltage value
8
indicated by Pi−1, and outputs a partial digital value
9
indicated by MiLi. The first partial analog voltage value
8
is connected to a partial A/D converter
12
. An output of the partial A/D converter
12
becomes the partial digital value
9
. The foregoing is the constructions of the pipeline stages.
Hereinafter, the operations of the i-th (first to fourth) pipeline stages will be described.
In each of the first to third pipeline stages
3
-
5
, the first offset addition unit
11
adds an offset voltage value equivalent to −0.5 LSB, as a first offset voltage value
17
, to the Pi−1 that is the inputted first partial analog voltage value
8
, and the A/D converter
12
performs A/D conversion on the Pi−1, thereby outputting, as the partial digital value
9
, [00,01,10] which are binary codes each corresponding to 1.5-bit output and having Mi as a higher-order bit and Li as a lower-order bit. Further, the partial D/A converter
13
performs D/A conversion on the partial digital value
9
, and the second offset addition unit
14
adds an offset voltage value equivalent to +0.5 LSB, as a second offset voltage value
18
, to a result of the D/A conversion. Then, the output from the second offset voltage value
18
and the first partial analog voltage value
8
are input to the subtracter
15
, and a difference voltage value between them is obtained, and the difference voltage value is amplified by the arithmetic amplifier
16
, thereby obtaining the Pi as the second partial analog voltage value
10
. The foregoing is the operation of each of the first to third pip

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