A/D converter correction scheme

Details A/D converter correction scheme A/D converter correction scheme

1998-11-12

2001-02-20

Young, Brian (Department: 2819)

Coded data generation or conversion

Converter compensation

Reexamination Certificate

active

06191714

ABSTRACT:

BACKGROUND
Many A/D converters suffer from a differential non-linearity error. This error may be caused by inaccuracy in capacitor sizing. This inaccuracy often causes missing codes in the output of the A/D converter. This results in granularity in the A/D converter and effectively reduces a dynamic range of the A/D converter output.
These missed codes often occur at the transition between most significant bits. For example, an incremental voltage beyond the voltage yielding the code 0111111 yields a code 1000011. This means that the codes between 0111111 and 1000011 are never used.
SUMMARY
The present system describes a highly linear N bit A/D converter system formed of an N+1 bit A/D converter and a memory. The A/D converter is purposely designed to miss codes, rather than repeat codes, when the most significant bits are turned off. The N+1 bits of output of the A/D converter is used to address a calibrated value in a look-up table in a memory that has N+1 address bits and N bits per word.


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patent: 5793319 (1998-08-01), Ard
patent: 5977894 (1999-11-01), McCarroll et al.

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