Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
1999-06-29
2001-09-11
Tokar, Michael (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S156000, C341S160000, C341S161000
Reexamination Certificate
active
06288662
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a pipeline type A/D converter circuit in which each sub-A/D converter and each sub-D/A converter of low bits are arranged as one block and a plurality of these blocks are cascade-connected, and to a configuration of a resistor ladder circuit for use in such a circuit.
Heretofore, there has been proposed the pipeline type A/D converter circuit technology in which each sub-A/D converter and each sub-D/A converter of low bits are arranged as one block and a plurality of these blocks are cascade-connected. The pipeline type A/D converter circuit is, for example, described in an article 1 of Lewis, S. H., and Gray, P. R., “A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter,” Proceeding of IEEE International Symposium on Circuits and Systems, pp. 954 to 961, 1987.
An example of a circuit configuration of a conventional pipelinetype A/D converter circuit is shown in FIG.
5
. In addition, an example of a configuration of a sub-A/D converter circuit which is used in each of blocks is shown in FIG.
6
. Also, an example of a conventional configuration of a resistor ladder for reference voltages of the sub-A/D converter circuit is shown in FIG.
7
. In this example, there is employed the sub-A/D converter circuit of 2 bits (four divisions). In addition,
FIG. 8
is a timing chart showing changes in signals with time in the conventional pipeline type A/D converter circuit.
In
FIG. 5
, a signal vin (FIG.
8
(
a
)) which has been inputted through an A/D converter circuit input terminal
17
is inputted, after having passed through a sample and hold circuit
1
, to both of a sub-A/D converter circuit
2
in the first stage and a multiplying D/A converter circuit (hereinafter, referred to as “an MDAC” for short, when applicable)
14
in the first stage. The signal which has been inputted to the sub-A/D converter circuit
2
is, as shown in
FIG. 6
, sent through a sub-A/D converter circuit input terminal
33
to one of non-inverting input terminals of comparators
21
,
22
and
23
. On the other hand, reference voltages
60
,
61
and
62
which are produced in a resistor ladder circuit shown in
FIG. 7
are respectively inputted through sub-A/D converter circuit reference voltage input terminals
34
,
35
and
36
to inverting input terminals of the comparators
21
,
22
and
23
. In
FIG. 7
, reference voltages
31
and
32
are divided through resistors
27
,
28
,
29
and
30
to produce the reference voltages
60
,
61
and
62
. In addition, the resistor ladder circuit shown in
FIG. 7
is commonly used in sub-A/D converter circuits
2
,
3
,
4
and
53
in the respective stages. In
FIG. 6
, after each of the comparators
21
,
22
and
23
has compared the electric potential at the sub-A/D converter circuit signal input terminal
33
with the electric potentials at the sub-A/D converter circuit reference voltage input terminals
34
,
35
and
36
corresponding to the respective comparators, the resulting output signals are inputted to an encoder
24
. The output signals from the encoder
24
are, after having been inputted to latches
25
and
26
, outputted through sub-A/D converter circuit output terminals
37
and
38
. After those output signals have been inputted to a sub-D/A converter circuit
5
shown in
FIG. 5
which converts in turn those signals into an analog voltage equivalent to the digital data of 2 bits, an output signal from the sample and hold circuit
1
is subtracted from the analog voltage signal in an addition circuit
11
. The output signal from the addition circuit
11
is amplified in an amplification circuit
8
to be inputted through an MDAC output terminal
18
to both of a sub-A/D converter
3
in the second stage and an MDAC
15
in the second stage. The waveform of the signal vout
1
at the MDAC output terminal
18
is shown in FIG.
8
(
b
).
The signal which has been inputted through the MDAC output terminal
18
to both of the sub-A/D converter circuit
3
in the second stage and the MDAC
15
in the second stage is processed in the same manner as that in the first stage to be inputted to both of a sub-A/D converter circuit
4
in the third stage and an MDAC
16
in the third stage. The waveform of the signal vout
2
at an MDAC output terminal
19
is shown in FIG.
8
(
c
).
The signal which has been inputted through the MDAC output terminal
19
to both of the A/D converter circuit
4
in the third stage and the MDAC
16
in the third stage is processed in the same manner as that in the first stage to be inputted to a sub-A/D converter circuit
53
in the fourth stage. The waveform of the signal vout
3
at an MDAC output terminal
20
is shown in FIG.
8
(
d
).
The output signals of the sub-A/D converter circuits
2
,
3
,
4
and
53
in the respective stages are fetched as the output of the A/D converter circuit through a digital correction circuit
52
.
SUMMARY OF THE INVENTION
However, since in the conventional pipeline type A/D converter circuit, as shown in
FIG. 8
, each of the MDAC output signals is largely increased simultaneously at a certain timing, there arises a disadvantage that the errors are added to one another in the respective stages so that the resulting large error is obtained.
When the DC gain of the operational amplifier which is employed in the MDAC is small, the error in the output of the MDAC becomes largest when the output voltage of the MDAC is greatly changed. For example, in FIG.
8
(
b
), it is assumed that the differential non-linear error (hereinafter, referred to as “a DNL error” for short, when applicable) of 0.8 LSB occurs at the timing the output voltage vout
1
is greatly changed (indicated by a dotted line) due to the small DC gain of the operational amplifier employed in the MDAC. Then, as shown in FIG.
8
(
c
), the output voltage vout
2
also is changed greatly at the same timing. Assuming that the magnitude of the voltage of the error which occurs due to the large output change in the output voltage vout
2
is equal to that in the case of the output voltage vout
1
and that the amplification degree of the amplification circuit
8
is
2
, then the DNL error which occurs in only the MDAC
15
in the second stage becomes half the DNL error which occurs in only the MDAC
14
in the first stage, i.e., 0.4 LSB. As a result, the DNL error in the output voltage vout
2
becomes the sum, 1.2 LSB, of the DNL error, 0.8 LSB, which occurs in only the MDAC
14
in the first stage and the DNL error, 0.4 LSB, which occurs in only the MDAC
15
in the second stage.
Likewise, assuming that the magnitude of the voltage of the error which occurs due to the large output change in the output voltage vout
3
is equal to that in the case of the output voltage vout
1
and also the amplification degree of the amplification circuit
9
is
2
, then the DNL error which occurs in only the MDAC
16
in the third stage becomes a quarter the DNL error which occurs in only the MDAC
14
in the first stage, i.e., 0.2 LSB. As a result, the DNL error in the output voltage vout
3
becomes the sum, 1.4 LSB, of the DNL error, 0.8 LSB, which occurs in the MDAC
14
in the first stage, the DNL error, 0.4 LSB, which occurs in only the MDAC
15
in the second stage and the DNL error, 0.2 LSB, which occurs in only the MDAC
16
in the third stage.
As described above, there arises a problem that if the output signals of each of the MDACs are changed simultaneously at a certain timing, then the errors in the respective stages are added to one another to provide the resulting large error.
In order to solve the above-mentioned problems associated with the prior art, according to the present invention, an A/D converter circuit is configured in such a way that the offset is obtained through a resistor ladder from which the reference voltages for comparators employed in sub-A/D converter are produced so that the difference occurs in the input/output characteristics between the sub-A/D converter in the first stage and each of the sub-A/D converters in and after the second stage. Sinc
Adams & Wilks
Seiko Instruments Inc.
Tan Vibol
Tokar Michael
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