A/D converter circuit

Details A/D converter circuit A/D converter circuit

2002-10-02

2004-03-16

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S154000

Reexamination Certificate

active

06707412

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based on application No. 2002-93878 filed in Japan, the contents of which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to high-speed operation of an A/D converter circuit.
2. Description of Related Art
FIG. 10
shows a conventional A/D converter, more precisely, it is a four-bit output type series-parallel A/D converter. The A/D converter includes: high-order comparators COMP
11
,
12
, and
13
controlled by control signals
1
A,
1
B, and
1
C, outputted from a high-order-comparator control circuit
10
; and low-order comparators COMP
21
,
22
, and
23
controlled by control signals
2
A,
2
B, and
2
C outputted from a low-order-comparator control circuit
20
. Input terminals (IN) of respective comparators COMP
11
,
12
and
13
, COMP
21
,
22
, and
23
are connected to an input terminal (AIN) of the A/D converter. To reference voltage terminals of the respective comparators, there are appropriately selected and inputted various levels of voltage obtained by dividing input voltage range of analog-input voltage VAIN (maximum reference voltage: VRH, minimum reference voltage: VRL) into sixteen by a ladder-resistance-element array.
The reference voltage terminals (REF) of the high-order comparators
11
,
12
, and
13
are connected to voltage-divided terminals (N
1
), (N
2
), and (N
3
), respectively, obtained by dividing the input voltage range of the analog-input voltage VAIN into four by the ladder-resistance-element array. At the time of A/D conversion, firstly, voltage level of the analog-input voltage VAIN is roughly detected and A/D conversion of high-order bits is conducted. Output terminals (
011
), (
012
), and (
013
) are connected to a switch selecting circuit
30
. From the switch selecting circuit
30
, there is selectively inputted any one of switch control signals S
1
through S
4
depending on an A/D conversion result of high-order bits.
The reference voltage terminals (REF) of the low-order comparators COMP
21
,
22
, and
23
are connected to voltage-divided terminals of the ladder-resistance-element array through a change-over switch groups SW
1
through SW
4
. The change-over switch groups SW
1
through SW
4
are alternatively selected in accordance with types of switch control signals S
1
through S
4
. Thereby, low-order reference voltage of the low-order comparators COMP
21
,
22
, and
23
is determined. That is, in case the analog-input voltage VAIN is same as or higher than high-order reference voltage VN
1
at a voltage-divided terminal of the ladder-resistance-element array, the change-over switch group SW
1
is selected and low-order reference voltages VN
01
, VN
02
, and VN
03
are inputted to the reference voltage terminals of the comparators COM
21
,
22
, and
23
, respectively. It should be noted that, in the precedent passage and following passages, voltage level of each voltage-divided terminal is indicated with a prefix “V” to a name of a voltage-divided terminal. Similar to the above case, in case the analog-input voltage VAIN is same as or higher than high-order reference voltage VN
2
and lower than VN
1
, the change-over switch group SW
2
is selected and low-order reference voltages VN
11
, VN
12
, and VN
13
are inputted. In case the analog-input voltage VAIN is same as or higher than high-order reference voltage VN
3
and lower than VN
2
, the change-over switch group SW
3
is selected and low-order reference voltages VN
21
, VN
22
, and VN
23
are inputted. In case the analog-input voltage VAIN is lower than VN
3
, the change-over switch group SW
4
is selected and low-order reference voltages VN
31
, VN
32
, and VN
33
are inputted.
A four-bit output can be obtained with the following manner. That is, bits of an output is divided into high-order bits and low-order bits and then, logic level of outputs
011
,
012
,
013
,
021
,
022
, and
023
from the comparators COMP
11
,
12
, and
13
, and the comparators COMP
21
,
22
, and
23
, respectively, are encoded.
FIG. 11
shows operational waveforms. The A/D converter of
FIG. 10
operates in synchronous with a clock signal CLK. The A/D converter takes a (½)-period of a clock signal CLK as a time step for its operation. Three operation states, namely, fetch operation of the analog input voltage VAIN (I), holding operation of the fetched voltage (II), and voltage comparison operation (III) are switched every time step. Time steps {circle around (
1
)} through {circle around (
5
)} make an operation unit and A/D conversion operation is conducted.
During a time step {circle around (
1
)}-{circle around (
2
)}, a high-order comparator COMP
1
x
(x=1, 2, and 3, same as the following descriptions) and a low-order comparator COMP
2
x
fetch the analog-input voltage VAIN (operation (I)). Voltage level fetched at this time step shifts to maximum voltage level VRH from voltage level VN
1
X that is same as or higher than high-order reference voltage VN
2
at a terminal (N
2
) of the ladder-resistance-element array and lower than high-order reference voltage VN
1
at the terminal N
1
. Capacitance components with respect to internal terminals of the comparators COMP
1
x
and COMP
2
x
are charged up to voltage level VRH for the analog-input voltage VAIN.
Next, during a time step {circle around (
2
)}-{circle around (
3
)}, each of the low-order comparators COMP
2
x
holds voltage level VRH (operation (II)), and each of the high-order comparators COMP
1
x
shifts to comparison state (operation (III)). Voltage level at internal terminals of respective high-order comparators COMP
1
x
makes transitions from the maximum voltage level VRH to respective high-order reference voltage VNx (x=1, 2, and 3, same as the following descriptions) through the reference voltage terminals (REF). As a result, from the reference voltage terminals (REF) of respective high-order comparators COMP
1
x
, there flows current due to charge and discharge from the capacitance components of the internal terminals.
FIG. 11
shows a case of the high-order comparator COMP
11
. Outflow current of peak current
1100
flows out due to discharge. The outflow current flows toward a terminal (RL) in the ladder-resistance-element array. Therefore, voltage rise in proportion to outflow current reflects level of the low-order reference voltage VN
01
at the voltage divided terminal (N
01
) as amount of voltage fluctuation. It is assumed that peak voltage corresponding to the amount of voltage fluctuation is V
100
.
Next, during a time step {circle around (
3
)}-{circle around (
4
)}, low-order reference voltage is set prior to comparison operation of respective low-order comparators COMP
2
x
. Based on comparison results of respective high-order comparators COMP
1
x
, a change-over switch group to be determined by the switch selecting circuit
30
is selected. In case of
FIG. 11
, change-over switch groups are changed from the change-over switch group SW
2
for voltage level VN
1
X at a precedent cycle to the changeover switch group SW
1
suitable to voltage level VRH. Due to changeover of the switch groups, capacitance components Cp
1
, Cp
2
, and Cp
3
between each of the change-over switch groups SW
1
through SW
4
and each of the low-order comparator COMP
2
x
are charged, whereby terminal voltage makes transition from voltage level VN
1
to VRH. At this stage, current is supplied from a terminal (RH). Consequently, low-order reference voltage VN
01
at the voltage-divided terminal (N
01
) is heightened. It is assumed that an amount of voltage fluctuation at this stage is V
2
. It should be noted that the capacitance components Cp
1
, Cp
2
, and Cp
3
are equivalent to a sum of parasitic capacitance components obtained at each of the change-over switch groups SW
1
through SW
4
, each of the low-order comparators COMP
2
x
, and wirings.
Further on, during a time step {circle around (
4
)}-{circle around (
5
)}, each of the high-order comparators COMP
1
x
keeps compar

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