A/D converter circuit

Details A/D converter circuit A/D converter circuit

2001-03-06

2002-10-01

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S158000

Reexamination Certificate

active

06459399

ABSTRACT:

FIELD OF THE INVENTION
The present invention in general relates to a chopper-type A/D converter circuit. More particularly, this invention relates to an A/D converter circuit capable of reducing power consumption by cutting off a through current of inverter circuits within comparators during a halt period of an A/D (analog to digital) conversion operation. In other words, the invention relates to an A/D converter circuit capable of setting an inverter circuit to a power-saving mode.
BACKGROUND OF THE INVENTION
FIG. 7
shows a structure of a conventional A/D converter circuit. This conventional A/D converter circuit
21
comprises a plurality of comparators
22
-
1
to
22
-M (where M represents a number of bits of a digital output of the A/D converter circuit
21
) each for comparing an input analog signal (an input voltage) input to the A/D converter circuit
21
from the outside with a predetermined reference voltage (a comparison voltage) by inputting the signal and the voltage into the comparator and for outputting a digital signal. Further, a ladder resistor circuit
23
is provided. This ladder resistor circuit
23
has a plurality of resistors
23
-
1
to
23
-(M+1) connected in series and having comparison-voltage input terminals (terminals for inputting a comparison voltage) of the comparators
22
-
1
to
22
-M connected to between these resistors. Further, a buffer circuit
24
having one end of the ladder resistor circuit
23
connected to an output terminal of the buffer circuit
24
, a buffer circuit
25
having the other end of the ladder resistor circuit
23
connected to an output terminal of the buffer circuit
25
, and a buffer circuit
26
having input-voltage input terminals (terminals for inputting input voltages) of the plurality of comparators
22
-
1
to
22
-M connected to an output terminal of the buffer circuit
26
, are provided.
FIG. 8
shows a detail structure of any comparator of the comparators shown in
FIG. 7. A
comparator
22
-
m
(which may be any comparator out of the comparators
22
-
1
to
22
-M) comprises a switch
31
having an input-voltage input terminal connected to one end of the switch
31
, a switch
32
having a comparison-voltage input terminal connected to one end of the switch
32
; a capacitor
33
having the other end of the switch
31
and the other end of the switch
32
connected to one end of the capacitor
33
; an inverter circuit
34
having the other end of the capacitor
33
connected to an input terminal of the inverter circuit
34
; and a switch
35
connected to between the input terminal of the inverter circuit
34
and an output terminal of the inverter circuit
34
.
FIG.
9
A and
FIG. 9B
are diagrams for explaining the operation of the conventional comparator
22
-
m
. Furthermore,
FIG. 10
is a waveform diagram showing the operation of the conventional comparator
22
-
m
. The comparator
22
-
m
repeats a state that the switches
31
and
35
are closed and the switch
32
is opened (refer to
FIG. 9A
) and a state that the switches
31
and
35
are opened and the switch
32
is closed (refer to FIG.
9
B), in synchronism with a clock signal input to the A/D converter circuit
21
from the outside. When the switch
31
is closed and the switch
32
is opened, an input voltage is applied to the input side (the side of the switches
31
and
32
) of the capacitor
33
. Then the voltage at the input side of the capacitor
33
becomes the input voltage having a voltage value Vin
2
.
When the switch
35
is closed, the input terminal of the inverter circuit
34
and the output terminal of the inverter circuit
34
are short-circuited. As a result, a threshold voltage Vth
2
of the inverter circuit
34
is generated at the input terminal and the output terminal of the inverter circuit
34
. In other words, a voltage at the output side (the inverter circuit
34
side) of the capacitor
33
and a voltage at the output side of the inverter circuit
34
become the threshold voltage Vth
2
. Thus, a charge of a potential difference between the voltage Vin
2
of the input voltage and the threshold voltage Vth
2
is accumulated in the capacitor
33
. On the other hand, when the switch
31
is opened and the switch
32
is closed, a comparison voltage is applied to the input side of the capacitor
33
. Then, the voltage at the input side of the capacitor
33
becomes the comparison voltage having a voltage value Vcomp2.
Further, when the switch
31
is opened and the switch
32
is closed, with the switch
35
opened, then the voltage at the output side of the capacitor
33
shifts by a change in the voltage at the input side of the capacitor
33
, “Vcomp
2
—Vin
2
”. In other words, the voltage at the output side of the capacitor
33
becomes “Vth
2
+(Vcomp
2
—Vin
2
)”. The voltage at the output side of the inverter circuit
34
becomes “Vth
2
+&agr;2”. In this case, &agr;2 is a product obtained by multiplying an amplification factor of the inverter circuit
34
to “Vcomp
2
—Vin
2
” that is the potential difference between the voltage at the output side of the capacitor
33
and the threshold voltage Vth
2
. An A/D conversion is executed based on the operation of each of the comparators
22
-
1
to
22
-M in a similar manner.
When the switches
31
and
35
are closed and the switch
32
is opened, the voltage at the output side of the capacitor
33
becomes the threshold voltage Vth
2
, and a through current flows to a transistor (not shown) inside the inverter circuit
34
. When the switches
31
and
35
are opened and the switch
32
is closed, the voltage at the output side of the capacitor
33
becomes close to the threshold voltage Vth
2
when “Vcomp
2
−Vin
2
”is not sufficiently large. Thus, the voltage at the output side of the inverter circuit
34
does not coincide with a high-potential side voltage VDD
2
of a power source or a low-potential side voltage GND
2
of the power source. Then, a through current flows to the transistor (not shown) within the inverter circuit
34
. In actual practice, “Vcomp
2
−Vin
2
”is not sufficiently large in most of the cases, and a through current flows as a result.
In other words, a through current flows in both the state that the switches
31
and
35
are closed and the switch
32
is opened and the state that the switches
31
and
35
are opened and the switch
32
is closed. The through current flows continuously even during a period while the clock signal has been stopped and the A/D conversion of the A/D converter circuit
21
has been in the halt. Therefore, there is an inconvenience that the power consumption of the A/D converter circuit
21
increases.
FIG. 11
is a diagram showing another conventional structure of a comparator for solving the above problem.
This comparator has a switch
40
provided between the output side of the capacitor
33
and a low-potential level side of a power source in the comparator
22
-
m
shown in FIG.
8
. An A/D converter circuit using this comparator keeps the switch
40
open during an A/D conversion operation. For stopping the A/D conversion, the switch
40
is closed. Thus, the voltage at the output side of the capacitor
33
becomes a low-potential side voltage GND
2
of the power source, and the through current of the inverter circuit
34
is cut off. Therefore, it is possible to realize a power-saving mode for reducing power consumption.
According to the above-described conventional technique, however, the switch
40
for the power-saving mode is added to the capacitor
33
within the comparator that substantially affects the precision of the A/D converter circuit. Therefore, there has been a problem that the potential of the comparator varies and the precision of the A/D converter circuit is degraded.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an A/D converter circuit capable of improving the precision of the A/D converter circuit while reducing power consumption.
The A/D converter circuit according to one aspect of the present invention comprises a switch un

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