A/D converter background calibration

Details A/D converter background calibration A/D converter background calibration

2001-03-14

2002-10-29

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S118000, C341S155000

Reexamination Certificate

active

06473012

ABSTRACT:

This application claims priority under 35 U.S.C. §§ 119 and/or 365 to 0000843-3 and 0003043 filed in Sweden on Mar. 14, 2000 and Aug. 29, 2000 respectively; the entire content of which is hereby incorporated by reference.
BACKGROUND
The present invention relates to a background calibrated analog-to-digital (A/D) converter and an A/D converter background calibration method.
This invention relates to A/D converters, and in particular how to reduce the distortion caused by background calibration of such converters. The maximum achievable accuracy-speed performance of any A/D-converter is limited by non-ideal effects associated with its building blocks. Typically, the performance is limited by settling time, finite amplifier gain and/or analog component mismatch. When designing high-speed, high-accuracy A/D converters, these limitations impose very stringent demands on the building blocks, leading to prolonged design time. It also requires the use of manufacturing processes that are optimized for component matching and performance, thus increasing the manufacturing cost. Many non-ideal effects can however be compensated for by calibration. See for example, U.S. Pat. No. 5,499,027, “Digitally self-calibrating pipeline analog-to-digital converter”. The problem is that the efficiency of the calibration may be degraded by drift and aging. Therefore, it is desirable to be able to continuously calibrate the A/D converter during normal operation. Many calibration schemes rely on some form of skip-and-fill method. See “Background Digital Calibration Techniques for Pipelined ADC's”, U.-K. Moon, and B.-S. Song, IEEE Trans. Circ. Syst.- II, pp. 102-109, Vol. 44, No. 2, February 1997, IEEE, and “A 15-b, 5-Msample/s Low-Spurious CMOS ADC”, S.-U. Kwak, B.-S. Song, and K. Bacrania, IEEE J. Solid-State Circ., pp. 1866-1875, Vol. 32, No. 12, December 1997, IEEE. In such methods, widely separated samples are skipped in the conversion and replaced by a fill sample usually calculated from interpolation of neighboring samples. At each skip, a calibration operation is performed. The error of the fill sample is seen as an increase in noise and/or spurious tones or frequency components in the output frequency spectrum. When the skip-rate is high, the fill-sample error is mainly represented by spurious tones, which is highly undesirable in, for example, telecommunications systems. Nevertheless it may sometimes be desirable to have a short re-calibration cycle (high skip-rate) in order to track more rapid changes in the operating conditions.
Another method for creating a calibration time-slot is found in “A 12b Digital-Background-Calibrated Algorithmic ADC with −90 dB THD”, O. E. Erdogan, P. J. Hurst, and S. H. Lewis, 1999 Intl. Solid-State Circ. Conf., pp. 316-317, February 1999, IEEE., where an input sample queue is formed by a cascade of sample-and-hold circuits. By emptying the queue slightly faster than it is filled, a calibration time-slot is occasionally available. Thus, this “input-queue” method has the benefit of creating a time-slot for calibration without the need to discard any samples. The main drawback of this method is that each extra sample-and-hold stage adds distortion and noise. Therefore, this approach is not optimal for high-speed, high-resolution A/D converters.
Thus, the key idea in most prior-art solutions is to replace every k
th
sample with a fill sample of slightly less quality. This is not a problem in most cases, if k is a large number. However, sometimes a shorter re-calibration cycle is desirable, as noted above. A short re-calibration cycle (small k) will, however, reduce the spurious-free dynamic range (SFDR) of the A/D converter. In some applications, for example telecommunication applications, it is usually preferred that errors degrade the signal-to-noise ratio (SNR) rather than the spurious-free dynamic range. Thus, if there is a need for background calibration with a short re-calibration cycle, it is necessary to find a better solution than to skip and fill every k
th
sample.
SUMMARY
The present invention addresses these and other concerns. A method and system is provided which provides frequent background calibration of an A/D converter without significant degradation of the spurious-free dynamic range.
According to one aspect, a background calibrated A/D converter includes a background calibrated analog-to-digital converter, with a random time interval generator adapted to initiate background calibration at randomly selected time instants to increase the spurious-free dynamic range of the A/D converter.
According to another aspect, a method of calibrating an A/D converter includes an A/D converter background calibration method, including the step of increasing the spurious-free dynamic range of an A/D converter by initiating background calibration at randomly selected time instants.
These and other aspects of the present invention make it possible to have a high average skip-rate, while maintaining a large spurious free dynamic range.


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