A/D converter and A/D converting method

Details A/D converter and A/D converting method A/D converter and A/D converting method

2000-11-15

2003-01-07

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S161000

Reexamination Certificate

active

06504500

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an analog-to-digital (A/D) converter and an A/D converting method, and more particularly, to a series-connected A/D converter, such as a successive approximation A/D converter, a cyclic comparison A/D converter, and a pipeline A/D converter.
An A/D converter converts an analog signal to a digital signal having n bits and typically includes a stage, which is referred to as a bit cell, and an analog block, which performs an n number of operations.
The analog block of a successive approximation A/D converter is provided with a single bit cell (stage). The output signal of the bit cell is fed back to the input terminal of the A/D converter. The bit cell performs an n number of operations to generate a digital signal having n bits.
The analog block of a cyclic comparison A/D converter has an m number (2≦m<n) of bit cells. The output of the last bit cell (bit cell number m) is fed back to the input terminal of the first bit cell. The bit cells perform an n/m number of operations to generate a digital signal having n bits.
The analog block of a pipeline A/D converter is provided with an n number of bit cells. Each of these bit cells performs a single operation to generate a digital signal having n bits.
FIG. 1
is a schematic block diagram showing a prior art bit cell
10
.
The bit cell
10
includes a sample-and-hold (S/H) circuit
11
, a single-bit analog-to-digital converter (ADC)
12
, a single-bit digital-to-analog converter (DAC)
13
, a subtractor
14
, and an amplifier
15
.
The S/H circuit
11
samples and holds an input signal IN. Then, the S/H circuit
11
provides the held analog signal Vin to the ADC
12
and the subtractor
14
.
The ADC
12
receives a median voltage ½Vref of a conversion range (input range) and compares the median voltage ½Vref with the analog signal Vin to generate a single-bit digital signal Dout. Then, the ADC
12
provides the digital signal Dout to the DAC
13
.
In response to the digital signal Dout, the DAC
13
generates an analog signal V
1
having the median voltage ½Vref or a potential of zero volts (V). The DAC
13
then provides the analog signal V
1
to the subtractor
14
.
The subtractor
14
subtracts the analog signal V
1
from the analog signal Vin and provides the amplifier
15
with the subtraction signal. The amplifier
15
has a gain of two and amplifies the subtraction signal to generate an amplified subtraction signal OUT.
FIG. 2
is a diagram illustrating an algorithm performed by the bit cell
10
, and
FIG. 3
is a diagram illustrating the operation of the bit cell
10
.
FIG. 4
is a graph showing the relationship between the analog signal of the bit cell
10
and a reference voltage.
FIG. 5
is a timing chart of the bit cell
10
.
The analog signal Vin provided from an external (i.e., previous) bit cell (stage) is compared with the median voltage ½Vref of the conversion range (step
21
). This generates a single-bit digital signal Dout of “0” or “1”. Then the digital signal Dout undergoes a mathematical operation of 2 (Vin−½×Vref) or 2×Vin (steps
22
,
23
). The operation result is transferred to the next bit cell.
However, the prior art method has the shortcomings listed below.
(a) An absolute median voltage ½×Vref must be generated. Further, a DAC is required to perform the mathematical operations and comparisons.
(b) The amplifier
15
, which has an amplification rate of two times, is required. This may produce an error during a mathematical operation that is caused by factors, such as the gain and offset of the amplifier
15
.
(c) The DAC
13
, which generates the signal V
1
having zero volts or the median voltage ½×Vref, is required. This may produce an error during operation that is caused by factors, such as the settling characteristic of the DAC
13
.
(d) The comparison between the absolute median voltage ½×Vref and the analog signal Vin may produce an error resulting from a sampling error produced during the high-speed comparison process.
(e) Settling error is produced as the speed of the operation process increases. This affects the A/D conversion accuracy.
The above shortcomings are described in detail in Ingino Jr., Joseph and Wooley, Bruce , A Continuously-Calibrated 10MSample/s 12b 3.3V ADC, ISSCC Digest of Technical Papers, Feb. 1998, pp. 144-145.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a highly accurate A/D converter and A/D conversion method that enable high-speed operation.
To achieve the above object, the present invention provides an A/D converter comprising a bit cell for converting an analog input signal to a single-bit digital signal. The bit cell includes an operational circuit for performing at least one of a first operation (Vin−VRH)+(Vin−VRL), and a second operation (VRH−Vin)+(VRL−Vin). VRH is a high potential reference voltage, VRL is a low potential reference voltage, and Vin is the voltage of the analog input signal.
A further aspect of the present invention provides an A/D converter comprising a bit cell for converting an analog input signal to a single-bit digital signal. The bit cell includes a first operational circuit for performing a first operation Vin−VRH to obtain a first operation result Va, a second operational circuit for performing a second operation Vin−VRL to obtain a second operation result Vb, and a third operational circuit connected to the first and second operational circuits to perform a third operation Va+Vb and obtain a third operation result. VRH is a high potential reference voltage, VRL is a low potential reference voltage, and Vin is the voltage of the analog input signal.
Another aspect of the present invention provides an A/D converter comprising a bit cell for converting an analog input signal to a single-bit digital signal. The bit cell includes a first operational circuit for performing a first operation VRH−Vin to obtain a first operation result Va, a second operational circuit for performing a second operation VRL−Vin to obtain a second operation result Vb, and a third operational circuit connected to the first and second operational circuits to perform a third operation Va+Vb and obtain a third operation result. VRH is a high potential reference voltage, VRL is a low potential reference voltage, and Vin is the voltage of the analog input signal.
A further aspect of the present invention provides an A/D converter comprising a bit cell for converting an analog input signal to a digital signal. The bit cell includes a sample-and-hold circuit for sampling and holding the analog input signal, a first operational circuit for obtaining the difference between a voltage of the sampled and held analog signal and a high potential reference voltage to generate a first differential voltage signal, a second operational circuit for obtaining the difference between the voltage of the sampled and held analog signal and a low potential reference voltage to generate a second differential voltage signal, a comparator connected to the first and second operational circuits to compare the first and second differential voltage signals, and a third operational circuit connected to the first and second operational circuit to add the first differential voltage signal and the second differential voltage signal to generate complementary first and second analog output signals. The comparator outputs one of the first and second analog output signals.
Another aspect of the present invention provides a method for converting an analog input signal to a digital signal. The method comprises the steps of computing a difference between the analog input signal and a high potential reference voltage to obtain a first operation result, computing a difference between the analog input signal and a low potential reference voltage to obtain a second operation result, computing a sum of the first and second operation results to obtain a third

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