A/D converter

Details A/D converter A/D converter

2002-09-04

2004-03-16

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

Reexamination Certificate

active

06707413

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an A/D converter for converting an analog signal into a digital signal, and more particularly to a parallel-type A/D converter.
2. Description of the Related Art
FIG. 10
is a diagram showing a structure of a conventional parallel-type A/D converter
800
. This conventional A/D converter
800
is used for performing high-speed analog-digital conversion.
The conventional A/D converter
800
includes a reference voltage generator circuit
801
, a differential amplifier array
802
, a comparator circuit array
803
, and an encoder circuit
805
. The reference voltage generator circuit
801
uses a plurality of resistors R
1
-R
n
for dividing a voltage, which is applied between terminals to which a top level reference voltage
801
a
and a bottom level reference voltage
801
b
are applied, so as to generate reference voltages VR
1
-VR
n+1
. The reference voltages VR
1
-VR
n+1
are input to the differential amplifier array
802
. The comparator circuit array
803
compares the reference voltages VR
1
-VR
n+1
with an analog signal voltage input via an analog signal voltage input terminal
804
in a parallel manner. The encoder circuit
805
performs logic processing (conversion) on comparison results output by the comparator circuit array
803
so as to output a digital data signal having a prescribed resolution.
A conventional A/D converter, such as the A/D converter
800
having the above-described parallel structure, has an advantage of performing high-speed A/D conversion as compared to other conventional A/D converters of various types, such as integrating-types, series-parallel types, etc. However, there is a disadvantage of the conventional A/D converter in that as resolving power thereof is increased, the number of differential amplifiers and comparator circuits included in the conventional A/D converter is required to be increased, and therefore power consumption and an area occupied by the differential amplifiers and the comparator circuits are increased.
Japanese Laid-Open Patent Publication No. 4-43718 discloses another conventional A/D converter
900
which is improved so as to overcome the above-described disadvantage.
FIG. 11
is a diagram showing a structure of the improved conventional parallel-type A/D converter
900
. The A/D converter
900
includes a reference voltage generator circuit
911
, a differential amplifier array
912
, an interpolation resistor array
916
, a comparator circuit array
903
, and an encoder circuit
905
. In the A/D converter
900
, the comparator circuit array
903
and the encoder circuit
905
have the same structure as corresponding elements of the A/D converter
800
of FIG.
10
. However, the A/D converter
900
is different from the A/D converter
800
in that the number of resistors included in the reference voltage generator circuit
911
is less than the number of those included in the reference voltage generator circuit
801
, the number of differential amplifiers included in the differential amplifier array
912
is less than the number of those included in the differential amplifier array
802
and the interpolation resistor array
916
is further included.
Specifically, the reference voltage generator circuit
911
uses m number of resistors R
1
-R
m
, which is less than the number required in accordance with the resolving power of the A/D converter
900
, for dividing a voltage, which is applied between terminals to which a top level reference voltage
911
a
and a bottom level reference voltage
911
b
are applied, so as to generate reference voltages VR
1
-VR
m+1
.
The differential amplifier array
912
uses m+1 differential amplifiers for amplifying voltage differences between each of the reference voltages VR
1
-VR
m+1
and an input analog signal voltage input via an analog signal voltage input terminal
904
, so as to output differential output voltages (non-inverted output voltages and inverted output voltages).
The interpolation resistor array
916
includes a plurality of resistors and divides a voltage, which is applied between terminals of two adjacent differential amplifiers to which non-inverted output voltages are applied, and a voltage, which is applied between terminals of two adjacent differential amplifiers to which inverted output voltages are applied, so as to be interpolated. Each of interpolated voltages derived from the non-inverted output voltages is compared with a corresponding one of interpolated voltages derived from the inverted output voltages by a corresponding comparator circuit included in the comparator circuit array
903
. The comparison results are converted into a digital code by the encoder circuit
905
so as to output a digital data signal.
In the A/D converter
900
, the voltage differences between each of the reference voltages VR
1
-VR
m+1
and the analog signal voltage are amplified by multiplying the voltage differences by a gain of the differential amplifier array
912
. Further, each comparator circuit included in the comparator circuit array
903
performs voltage comparison on corresponding output voltages of two adjacent differential amplifiers, which are interpolated by the interpolation resistor array
916
, and therefore the number of differential amplifiers can be reduced to 1/x, where x is the number of interpolated bits, as compared to the case where the interpolation processing is not performed. Therefore, it is possible to reduce the power consumption and area occupied by the differential amplifiers to some extent.
A comparator circuit which can be used in both the A/D converter
800
of FIG.
10
and the A/D converter
900
of
FIG. 11
is shown in FIG.
12
.
FIG. 12
is a circuit diagram of a comparator circuit
850
for use in a conventional A/D converter.
The comparator circuit
850
compares voltage Vo applied to a gate of an NMOS transistor m
1
with voltage Vob applied to a gate of an NMOS transistor m
2
.
When Vo>Vob, a drain current (Id1) of the NMOS transistor m
1
is greater than a drain current (Id2) of the NMOS transistor m
2
. In this case, output voltages of the comparator circuit
850
are determined by load resistance (RL) and the drain currents (Id1 and Id2). The relationship between the determined output voltages of the comparator circuit
850
is represented by Q (=VDD−Id1·RL)<QB(=VDD−Id2·RL).
When Vo<Vob, the drain current (Id2) of the NMOS transistor m
2
is greater than the drain current (Id1) of the NMOS transistor m
1
. The relationship between the output voltages of the comparator circuit
850
is represented by Q>QB.
However, even in the case where an A/D converter is configured so as to use the interpolation resistors for interpolating and comparing voltages amplified by the differential amplifiers in the above-described manner, the number of comparator circuits included in the A/D converter is required to comply with the requirements of the resolving power of the A/D converter. Specifically, 2
n−1
comparator circuits are required when the A/D converter outputs an n-bit digital code. Therefore, the A/D converter has a problem that as the resolving power of the A/D converter is increased, the number of comparator circuits included in the A/D converter is considerably increased, thereby increasing power consumption of the A/D converter.
One of techniques of reducing power consumption of a comparator circuit itself is known from Thomas Byunghak Cho, “A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 3, MARCH 1995, pp. 166-172. This publication describes that dynamic comparator circuits are used in a low-resolution A/D conversion section which is provided in each pipeline stage of a pipeline A/D converter, instead of using high-speed and highly-responsive constant current-type comparator circuits for use in a typical A/D converter. Since the dynamic comparator circuit does not require a constant current, the power consump

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