A/D converter

Details A/D converter A/D converter

2003-06-20

2004-03-30

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S144000, C341S145000, C341S172000

Reexamination Certificate

active

06714151

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
The application is based upon and claims the benefit of priority from the prior Japanese Patent Application Nos. 2002-233561, filed on Aug. 9, 2002 and 2002-181742, filed on Jun. 21, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an A/D converter (analog/digital converter) for converting an inputted analog signal into a digital signal, and is particularly suitable for being used for a successive approximation type A/D converter for converting an analog signal into a digital signal by a successive comparison operation.
2. Description of the Related Art
A successive approximation type A/D converter is presently known as an A/D converter, which can be realized with a simple circuit constitution and produced at comparatively low cost with high matching property with a CMOS process, requires less time for A/D conversion that is the conversion processing from an analog signal to a digital signal, and has a wide range of product uses. In the successive approximation type A/D converters, the one using a double stage DAC (a D/A converter: a digital/analog converter) for converting a comparison digital signal into a comparison analog signal can realize an A/D converter (: an analog/digital converter) with high resolution in a small mounting area.
A successive approximation type A/D converter using the double stage DAC is constituted of a double stage DAC constituted of a main DAC for deciding a most significant bit (MSB) side and a sub DAC for deciding a least significant bit (LSB) side, a comparator circuit, and a control circuit (control method) called an “SAR (successive approximation register)”. At first, an analog potential set by the main DAC and an input analog potential are compared, whereby high-order bits are decided. The analog potential set by the main DAC corresponding to the decided high-order bits and the analog potential set by the sub DAC are added, and a sum of them and the inputted analog potential are compared, whereby low-order bits are decided.
The double stage DACs are broadly divided into four constitutions (the main DAC+the sub DAC) as shown below depending on whether the main DAC and the sub DAC are realized by capacitor arrays, or resistor strings.
(1) Capacitor array+capacitor array type (hereinafter, called C-C type)
(2) Resistor string+capacitor array type (hereinafter, called R-C type)
(3) Capacitor array+resistor string type (hereinafter, called C-R type)
(4) Resistor string+resistor string type (hereinafter, called R-R type)
Constitution examples of a successive approximation type A/D converter using a C-R type double stage DAC are disclosed in, for example, Japanese Patent Laid-open No. 59-163913 and Japanese Patent Laid-open No. 57-55614.
A conventional successive approximation type A/D converter using a C-R type double stage DAC will be explained hereinafter.
FIG. 1
is a diagram showing a circuit constitution of the conventional successive approximation type A/D converter.
The successive approximation type A/D converter in
FIG. 1
includes an input terminal
3
to which an input potential Vin is applied, nodes
24
to
27
, nodes
40
to
44
, a switch circuit
21
, a switch circuit
22
, a switch circuit
23
, a switch circuit
121
, a comparator
30
, a successive approximation control circuit
32
′, resistors R
0
to R
15
, and capacitors C
1
to C
5
. The successive approximation control circuit
32
′ controls an operation of each of the switch circuits
21
,
22
,
23
,
121
, and the like.
The resistors R
0
to R
15
and the switch circuit
121
constitute a 4-bit sub DAC, and the capacitors C
1
to C
5
and the switch circuit
21
(and
22
and
23
) constitute a 4-bit main DAC. As for the capacitors C
1
to C
5
constituting the main DAC, if a capacitance value of each of C
1
and C
2
is assumed to be Cx, C
3
is weighted to be 2Cx, C
4
is weighted to be 4Cx and C
5
is weighted to be 8Cx. To secure relative accuracy, the sampling capacitors C
3
to C
5
are generally realized by connecting, for example, two, four or eight of certain unit capacitors Cx in parallel.
When sampling is performed, all of the capacitors C
1
to C
5
are connected to an analog input terminal
3
(Vin) via the switch circuit
21
, the node
25
and the switch circuit
22
, and charged to the input potential Vin. In this situation, the switch
23
is controlled so that the node
24
is at GND.
After sampling is finished, a comparison operation is started, and digital data corresponding to the input potential Vin is decided in sequence from the MSB. More specifically, the switch
23
is opened to bring the node
24
into a floating state, for example, the nodes
40
to
43
are connected to the GND via the switches
21
and
22
, and the node
44
is connected to a reference potential Vref (a terminal
1
). By the connection, electric charge stored by the input potential Vin at the sampling time is redistributed to the sampling capacitors Cl to C
5
, and a potential of the node
24
becomes (Vref/2−Vin) The node
24
is connected to an input of the comparator
30
, and it can be determined according to a potential of the node
26
being an output of the comparator
30
whether the analog input potential Vin is larger or smaller than ½ of the reference potential Vref.
In the above-described connection, the node
44
is connected to the reference potential Vref, and the other nodes
40
to
43
are connected to the GND. Namely, 8Cx of C
5
are connected to the reference potential Vref, and the sum total of 8Cx of the remaining C
1
to C
4
are connected to the GND. Generally, when the number of unit capacitors Cx connected to the reference potential Vref is assumed to be m, and the number of the remaining unit capacitors Cx connected to the GND is assumed to be (16−m), the potential Vx of the node
24
is
Vx=
(
m/
16)
Vref−Vin.
For example, when the node
41
is connected to Vref, and the remaining nodes
40
,
42
,
43
and
44
are connected to the GND, m equals 1, and therefore the potential of the node
24
is (Vref/16−Vin).
Accordingly, by successively changing m, it is possible to change the potential of the node
24
successively in increments of Vref/16, and the MSB side of the digital data (high-order 4 bits) can be decided.
Next, with m that is decided as described above being assumed to be m′, m′ of the unit capacitors Cx out of C
2
to C
5
are connected to the reference potential Vref, the remaining (15−m′) of the unit capacitors Cx out of C
2
to Cs are connected to the GND, and the node
40
of one of the unit capacitor Cx of C
1
is connected to the sub DAC (R
0
to R
15
, and the switch circuit
121
). The potential of the node
40
is changed in increments of Vref/16 by the sub DAC, whereby the potential of the comparator input
24
can be changed in increments of Vref/256. Consequently, the LSB side of the digital data (low-order 4 bits) is decided, and 8-bit digital data in total can be obtained.
FIG. 2
is a diagram showing another circuit constitution of the conventional successive approximation type A/D converter.
In
FIG. 2
, capacitors C
1
to CS and a switch group
21
(switches SWC
1
to SWC
5
) constitute a capacitor type DAC (main DAC) with 4-bit accuracy, and resistors R
0
to R
15
and a selector
121
constitute a resistor type DAC (sub DAC) with 4-bit accuracy. As for the capacitors C
1
to CS, if the capacitance value of each of the capacitors Cl and C
2
is Cx, a capacitance value of the capacitor C
3
is weighted to 2Cx, a capacitance value of the capacitor C
4
is weighted to 4Cx (=2
2
Cx) , and a capacitance value of the capacitor CS is weighted to 8Cx (=2
3
Cx) The capacitors C
3
, C
4
and CS are generally constituted by connecting, for example, two, four, and eight of the unit capacitors Cx in parallel, respectively, to secure relative accuracy. Resistance values of

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