A/D converter

Details A/D converter A/D converter

2001-01-17

2003-06-24

JeanGlaude, Jean Bruner (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S164000, C341S108000

Reexamination Certificate

active

06583745

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an A/D converter incorporated in a single-chip microcomputer and the like.
2. Description of the Prior Art
FIG. 9
is a block diagram showing an A/D converter using a conventional sequential conversion method. In
FIG. 9
, reference numeral
1
denotes a capacitor;
2
indicates an inverter connected in series to the capacitor
1
;
3
,
4
, and
5
each denote switches for controlling charging/discharging of the capacitor
1
; and
6
denotes a comparator composed of the components described above. Reference numeral
7
indicates a successive approximation register for sequentially holding the output of the comparator
6
;
8
denotes a ladder resistor composed of a plurality of resistors connected in series for dividing a reference voltage VREF and generating various comparison voltages while
9
denotes a decoder for selecting from comparison voltages generated by the ladder resistor
8
. A combination of the ladder resistor
8
and the decoder
9
functions as a D/A converter for converting digital data from the successive approximation register
7
, into analog voltages. Reference numeral
10
indicates an input terminal for receiving the first A/D input while
11
indicates an input terminal for receiving the second A/D input;
12
and
13
each denote a switch for selecting the A/D inputs; and
14
denotes a selection circuit composed of the switches
12
and
13
;
15
denotes an A/D control circuit for controlling the comparator
6
, the successive approximation register
7
, and the input selection circuit
14
described above.
Next, the operation of the A/D converter will be described.
In the sampling mode, the A/D control circuit
15
controls the input selection circuit
14
so that the switch
12
is turned ON and the switch
13
is turned OFF in order to charge the capacitor
1
by the first A/D input applied to the input terminal
10
. At that time, in the comparator circuit
6
, the switch
4
is OFF while the switches
5
and
3
are ON. Then, the A/D converter assumes the hold mode in which the switch
12
is turned OFF to disconnect the first A/D input and hold the charge voltage of the capacitor
1
for a certain period of time. During this period, the comparator
6
turns ON the switch
4
and turns OFF the switches
5
and
3
so as to receive a comparison voltage from the decoder
9
and compares it with the charge voltage of the capacitor
1
. This comparison voltage is sequentially changed to perform first A/D conversion of the first A/D input applied to the input terminal
10
.
After the A/D conversion of the first A/D input has been completed, the switch
4
is turned OFF and the switches
5
and
3
are turned ON in the comparator
6
while the switch
12
is turned OFF and the switch
13
is turned ON in the input selection circuit
14
, so as to charge the capacitor
1
by the second A/D input applied to the input terminal
11
. Then, the switch
13
is turned OFF to disconnect the second A/D input and hold the charge voltage of the capacitor
1
for a certain period of time. During this period, the comparator
6
turns ON the switch
4
and turns OFF switches
5
and
3
, and compares a comparison voltage received| from the decoder
9
with the charge voltage of the capacitor
1
. Thus, first A/D conversion of the second A/D input applied to the input terminal
11
is performed.
The second and later conversions of the first and second A/D inputs are performed in the same way as that described above, that is, by sequentially selecting the switches
12
and
13
of the input selection circuit
14
, and the switches
4
,
5
, and
3
of the comparator
6
so as to sample and hold the first and the second A/D inputs alternately. Thus, in the scan mode, a plurality of A/D inputs are converted into digital data by a single A/D converter using a time-division method.
Incidentally, conventional A/D converters as explained above are described in, for example, JP-A Nos. 4-7914(1992), 10-145196 (1998), and 58-12424 (1983).
Since the conventional A/D converter is configured as described above, when the sample/hold functions are used in the scan mode, an electric charge on the capacitor
1
is discharged to the line to the input terminal
11
at the time of selection from the first A/D input (on line
10
) to the second A/D input (on line
11
), which produces noise onto the line connecting between the input selection circuit
14
and the switch
5
of the comparator
6
, thereby lowering A/D conversion accuracy in an A/D converter incorporated in a single-chip microcomputer.
SUMMARY OF THE INVENTION
The present invention is implemented to solve the foregoing problem. It is therefor an object of the present invention to provide an A/D converter capable of reducing noise produced at the time of selection from the first A/D input to the second A/D input so as to enhance A/D conversion accuracy.
According to one aspect of the present invention, there is provided an A/D converter such that a successive approximation register has a plurality of A/D registers each corresponding to one of the A/D inputs, and that A/D conversion of an A/D input is controlled after the capacitor in a comparator is charged by a voltage determined based on a value held by the A/D register corresponding to the A/D input to be A/D converted.
Here, A/D conversion of an A/D input may be performed after the capacitor in a comparator is charged by a voltage corresponding to a previous A/D conversion value held by the corresponding A/D register.
First A/D conversion of an A/D input may be performed after the capacitor in a comparator is charged by a half of a reference voltage determined based on a value held by the corresponding A/D register.
When the capacitor in a comparator is charged, parasitic capacitances may be also charged at the same time.
A/D conversion of an A/D input may be initiated a predetermined period of time after the capacitor in a comparator is charged by the A/D input voltage.
A time adjustment register may be provided in which time taken before A/D conversion is initiated is set.
A/D conversion of an A/D input may be initiated after charging parasitic capacitances.
Each switch employed may be controlled according to data set in a wiring connection selection register, and further A/D conversion may be initiated after charging wiring determined as a result of the control.


REFERENCES:
patent: 4454500 (1984-06-01), Kato et al.
patent: 5331324 (1994-07-01), Nakajima
patent: 5585796 (1996-12-01), Svensson et al.
patent: 5619201 (1997-04-01), Imakura
patent: 5877719 (1999-03-01), Matsui et al.
patent: 6181268 (2001-01-01), Miyake et al.
patent: 6181269 (2001-01-01), Nishiuchi et al.
patent: 6239734 (2001-05-01), Bae et al.
patent: 6304203 (2001-10-01), Yamada
patent: 58-12424 (1983-01-01), None
patent: 4-7914 (1992-01-01), None
patent: 10-145196 (1998-05-01), None

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