A/D converter

Details A/D converter A/D converter

2001-12-13

2003-04-01

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000, C341S143000, C341S118000, C341S120000, C341S144000

Reexamination Certificate

active

06542105

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an A/D converter for converting an analog input signal into a digital signal, and an image pickup apparatus employing the same.
2. Related Background Art
FIG. 13
is a circuit block diagram showing a configuration of a conventional A/D converter. In
FIG. 13
, there is shown an example of an A/D converter wherein a counter
1
and a D/A converter
2
are employed as a ramp waveform generator, and an analog input signal is compared with an output signal of the D/A converter
2
in a comparator
3
, thereby carrying out the A/D conversion for the analog input signal. For example, a basic clock signal is inputted to the counter
1
, and then the counter
1
carries out the counting-up from zero. The magnitude of an output signal of the D/A converter
2
is also increased along with the counting-up and becomes equal to the magnitude of the analog input signal which is being inputted to the comparator
3
, at a certain time so that the polarity of the output signal of the comparator
3
is inverted. The A/D conversion is carried out in such a way that the output signal of the comparator
3
is used to control the operation of the counter
1
, and at the time when the polarity of the output signal of the comparator
3
is inverted, the operation of the counter
1
is stopped so that the digital output signal thereof becomes the digital value corresponding to the analog input signal.
FIG. 14
is a circuit block diagram showing a configuration of an example of a solid-state image pickup apparatus in which the A/D converter shown in
FIG. 13
is used for the A/D conversion of a sensor output. The A/D converter is constituted of a counter
1
, a D/A converter
2
, a comparator
3
and an oscillator
4
, and this A/D converter is connected to every vertical signal line
6
. The sensor has a structure in which sensor cells
5
are arranged in a matrix form of n (row)×m (column) to construct the two-dimensional sensor, and the sensor outputs which are connected to the associated one of the vertical signal lines are transferred to the A/D converter, which is provided in every vertical signal line, by a vertical shift register
7
. The counter
1
which has received a clock signal from the oscillator
4
, for example, carries out the counting operation from zero, and the output of the D/A converter
2
which receives the digital output therefrom is connected to one of inputs of the comparator
3
the other of which is connected to the associated one of the vertical signal lines
6
. Therefore, the analog output voltage is increased along with the counting-up by the counter
1
, and at the time when the analog output voltage becomes equal to the magnitude of the sensor output signal, the polarity of the output signal of the comparator
3
is inverted to drive the register
8
in such a way as to store the digital value of the counter
1
at this time. The digital value stored in the associated one of the registers
8
corresponds to the A/D conversion result of each of the sensors, and the digital value thereof is outputted through a terminal
9
.
In this conventional A/D converter, the settling time of the output signals of the D/A converter becomes normally longer than a period of time which is the minimum time required for the operation of one count of the counter. For this reason, a period of time required for the comparison operation in the comparator
3
also becomes long along with the increase of the setting time, and hence the conversion speed in the A/D converter is limited by the D/A converter. As a result, there arises the problem in that it is difficult to enhance the conversion speed.
FIG. 15
is a timing chart showing the clock signal inputted to the counter
1
and the output voltage of the D/A converter
2
which is changed along with the input of the clock signal. It is understood from
FIG. 15
that a minimum value of the cycle of the clock signal is limited by the settling time of the D/A converter
2
.
In addition, if the clock frequency of the counter
1
is increased barely up to the settling time of the D/A converter
2
, then the D/A converter
2
is easy to be influenced by the switching noise generated by the counter
1
as the digital circuit. Then, when the difference in magnitude between the output signal of the D/A converter
2
and the analog input signal is small, there also arises the problem in that the possibility that the comparator
3
causes the malfunction due to the switching noise becomes high. In particular, when the sensor as shown in
FIG. 14
is employed, the digital circuits which generate the switching noises, such as the register and the counter, may be disposed close to the sensor in many cases. As a result, there arises the problem in that the sensor suffers the influence of the noise to degrade the S/N ratio.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an A ID converter which is capable of enhancing the A/D conversion speed while maintaining the A/D conversion accuracy, and an image pickup apparatus employing the same.
In order to attain the above-mentioned object, according to one aspect of the present invention, there is provided an A/D converter comprising:
a counter arranged to count a clock signal to output a digital signal corresponding to an analog input signal;
a D/A converter arranged to convert the output signal of the counter into an analog signal;
a comparator arranged to compare the analog input signal with the output signal of the D/A converter to control the counter in accordance with the comparison result; and
a clock supply circuit arranged to supply the counter with the clock signal,
wherein the frequency of the clock signal is changed in accordance with a difference signal exhibiting the difference between the analog input signal and the output signal of the D/A converter.
Also, according to another aspect of the present invention, there is provided an A/D converter comprising:
a counter arranged to count a clock signal to output a digital signal corresponding to an analog input signal;
a D/A converter arranged to convert the output signal of the counter into an analog signal;
a comparator arranged to compare the analog input signal with the output signal of the D/A converter to control the counter in accordance with the comparison result; and
a clock supply circuit arranged to supply the counter with the clock signal,
wherein the D/A converter includes an output amplifier, and a bias current which flows through the output amplifier is changed in accordance with a difference signal exhibiting the difference between the analog input signal and the output signal of the D/A converter.
Also, according to another aspect of the present invention, there is provided an A/D converter comprising:
a counter arranged to count a clock signal to output a digital signal corresponding to an analog input signal;
a D/A converter arranged to convert the output signal of the counter into an analog signal;
a comparator arranged to compare the analog input signal with the output signal of the D/A converter to control the counter in accordance with the comparison result; and
a clock supply circuit arranged to supply the counter with the clock signal,
wherein an output impedance of a gate circuit which is included in at least one of the counter and the clock supply circuit is changed in accordance with a difference signal exhibiting the difference between the analog input signal and the output signal of the D/A converter.
Other objects and features of the present invention will be apparent from the following specification and the figures.


REFERENCES:
patent: 4496937 (1985-01-01), Kitagawa et al.
patent: 4996529 (1991-02-01), Connell
patent: 5262780 (1993-11-01), Gray
patent: 5568141 (1996-10-01), Mori
patent: 5883590 (1999-03-01), Sugden et al.
patent: 5920274 (1999-07-01), Gowda et al.
patent: 6373266 (2002-04-01), Carelli et al.

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