Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2000-03-03
2002-06-25
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S118000
Reexamination Certificate
active
06411241
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an A/D converter which is provided as a peripheral circuit of a microprocessor and the like, and converts an analog input from an analog value to a digital value.
BACKGROUND OF THE INVENTION
FIG. 2
shows a block diagram of an A/D converter built in a conventional microprocessor. In
FIG. 2
,
1
is the body of the A/D converter.
101
is an S/H circuit for performing a sample holding operation of an input analog signal. A higher bit A/D conversion unit
102
and a lower bit A/D conversion unit
103
convert an input analog signal into a digital signal. The lower bit A/D conversion unit
103
stops the operation according to an operation stop signal.
FIG. 3
shows a timing chart of the operation of a conventional A/D converter. In
FIG. 3
, a normal conversion mode is shown in a second stage, and a saving conversion mode for reduced bits is shown in a third stage. In the saving conversion mode, only the higher bit A/D conversion unit
102
performs a converting operation with the operation of the lower bit A/D conversion unit
103
suppressed.
Described below will be the operation of the conventional A/D converter having the above described configuration.
The A/D converter
1
has two operation modes. One is the normal operation mode in which both higher and lower bits are converted. The other is the conversion mode for reduced bits in which only higher bits are converted.
In the normal operation mode, an input analog signal is sample-held by the S/H circuit
101
, and the sample-held analog signal is processed in the analog-to-digital converting operation for higher bits by the higher bit A/D conversion unit
102
. Then, lower bits are processed in the analog-to-digital converting operation by the lower bit A/D conversion unit
103
, thereby outputting a digital conversion value.
In the conversion mode for reduced bits, an input analog signal sample-held by the S/H circuit
101
is processed in the analog-to-digital converting operation only by the higher bit A/D conversion unit
102
. At this time, the lower bit A/D conversion unit
103
stops its operation according to the operation stop signal. Stopping the lower bit A/D conversion unit
103
lowers the conversion precision, but the electric power can be saved.
FIG. 4
shows an example of the conventional A/D converter.
In
FIG. 4
, S/H circuits
201
and
202
perform a sample holding operation on an analog signal. A subtraction circuit
203
performs a subtracting operation on an input analog signal, and outputs a difference. An A/D conversion unit includes a higher bit conversion unit
240
and a lower bit conversion unit
250
. The higher bit conversion unit
240
performs an analog-to-digital converting operation on higher bits while the lower bit conversion unit
250
performs an analog-to-digital converting operation on lower bits. A stop control signal is input to the lower bit conversion unit
250
. When the stop control signal is valid, the lower bit conversion unit
250
stops its operation.
The higher bit conversion unit
240
and the lower bit conversion unit
250
further include the following components. That is, A/D conversion units
210
and
212
convert analog signals into m- and n-bit digital signals respectively. A D/A conversion unit
211
converts an m-bit digital signal into an analog signal. A register
220
stores m-bit digital data. A digital adder
230
outputs an (m+n) bit digital signal by adding m higher bits and n lower bits.
Described below will be the operation of the conventional A/D conversion unit with the above described configuration.
First, an analog signal reproduced by the S/H circuit
201
is converted into m higher bits digital signal by the A/D conversion unit
210
in the first stage. Next, in the normal operation mode, the S/H circuit
201
obtains the difference between the analog signal reproduced by the S/H circuit
201
and the analog signal reproduced by the D/A conversion unit
211
through the subtraction circuit
203
. After the result is sample-held by the S/H circuit
202
, it is converted into a digital signal of n lower bits by the A/D conversion unit
212
at the subsequent stage. Finally, an (m+n) bit digital signal is obtained by adding the m higher bits temporarily stored by the register
220
and the n lower bits converted by the A/D conversion unit
212
.
In addition, in the electric power saving operation for reduced bits, the lower bit conversion unit
250
is stopped according to the stop control signal, and the converting operation is performed by the S/H circuit
201
, the higher bit conversion unit
240
, and the digital adder
230
.
There is a method for stopping a circuit for reducing power consumption in an A/D converter as a peripheral circuit mounted in a microprocessor, etc.
However, to reduce the power consumption with the conversion precision maintained, the conventional technology shown in
FIG. 2
has the problem that the effect of reducing power consumption works only in a standby state, and that the conversion precision is lowered in the saving mode.
The present invention has been developed based on the above described background, and aims at providing an A/D converter for realizing both reduction of power consumption and guarantee of the conversion precision.
SUMMARY OF THE INVENTION
To solve the above described problems, the A/D converter according to a first aspect of the present invention has a configuration in which a difference between previously input and currently input analog signals is processed in the analog-to-digital converting operation, added to an A/D converted value of the previously input analog signal, and is then output. A difference of a smaller value can be processed in the analog-to-digital converting operation with the conversion precision maintained.
In addition, the A/D converter according to a second aspect of the present invention includes a plurality of A/D conversion units, stores analog signals input to the plurality of A/D conversion units and digital signals converted, and stops part of the A/D conversion units. Then, only the remaining A/D conversion units A/D convert the differences (that is, the signals sequentially obtained by subtracting the reference analog signals stored previously in a time series from the current analog signals), add the results to the stored digital signals, and then output the sums. Since only the remaining conversion units perform the converting operations while part of the A/D conversion units are in the inactive state, the electric power can be saved by the amount supposed to be consumed by the inactive A/D conversion units. Furthermore, since all bit conversion values stored at the reference point are added to the output digital signal obtained after the A/D conversion of the change in time series of the input analog signal based on a signal at a reference point, the conversion precision can also be maintained.
In addition, to solve the above described problems, the A/D converter according to a third aspect of the present invention further adds an analog subtraction circuit and a selector to the conventional A/D converter. With the configuration and by converting a voltage change of an input analog signal only by a lower bit A/D conversion circuit, power consumption can be reduced with the conversion precision successfully maintained.
Furthermore, to solve the above described problems, the A/D converter according to a fourth aspect of the present invention has a unit for detecting the overflow of conversion result of the lower bit A/D conversion circuit, added to the configuration of the above described first aspect of the present invention. With this configuration, in addition to the effect of the first aspect of the present invention, the converting operation can be optimized, thereby further reducing the power consumption.
REFERENCES:
patent: 4654635 (1987-03-01), Van De Plassche
patent: 5148166 (1992-09-01), Ribner
patent: 5864310 (1999-01-01), Khorramabadi
patent: 06085672 (1994-03-01), None
Jeanpierre Peguy
Lauture Joseph
Matsushita Electric Industrial Co., Inc.
Parkhurst & Wendel LLP
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