Coded data generation or conversion – Analog to or from digital conversion – Analog to digital conversion
Reexamination Certificate
2001-10-09
2002-10-15
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Analog to digital conversion
C341S157000
Reexamination Certificate
active
06466151
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an A/D converter for converting a voltage of an analog input voltage signal to digital data.
2. Description of the Prior Art
An A/D converter for converting a voltage of an analog input voltage signal to digital data with a ring gate delay circuit is known. The same inventor of the present invention disclosed this prior art A/ID converter in U.S. Pat. No. 5,396,247. The ring gate delay circuit is also referred to as a pulse circulating circuit. The pulse circulating circuit includes a plurality of inverting circuits connected in series in a ring to circulate a pulse to repeatedly output the pulse. This A/D converter has no special analog circuit, so that the circuit area on a substrate of an integrated circuit can be reduced.
FIG. 16
is a block diagram of this prior art A/D converter
100
. This prior art A/D converter
100
includes the pulse circulating circuit (ring gate delay circuit)
110
, an input terminal
102
a
, a counter
112
, a pulse position detection circuit
116
, an encoder
118
, a signal processing circuit
119
and a control circuit
104
.
The pulse circulating circuit
110
includes a plurality of inverting circuits (a NAND gate and inverters) connected in series in a ring to circulate a pulse to repeatedly output the pulse in response to a pulse signal PA. The NAND gate in the pulse circulating circuit
110
has a control input to control generation of the pulse. Each inverting circuit successively shifts an edge of the pulse to the next one with delay which varies in accordance with a supply voltage thereto, that is, the analog input voltage signal Vin.
The counter
112
counts the pulses and outputs binary count data. On the other hand, the pulse position detection circuit
116
detects a position of one of the inverting circuits outputting an edge of the pulse in response to a pulse signal PB. The encoder
118
encodes the position into a binary data. The control circuit
104
generates the pulse signal PA supplied to the control input of the NAND gate in the pulse circulating circuit
110
to operate the pulse circulating circuit. After a predetermined interval from generation of the pulse signal PA, the control circuit
104
generates the pulse signal PB supplied to the pulse position detection circuit to detect the position. The outputting circuit
119
outputs A/D conversion data including the binary count data as upper bits and the binary data as lower bits.
In this prior art A/D converter, although U.S. Pat. Ser. No. 5,396,247 did not specifically describe that the analog input voltage signal was supplied to circuits other than the pulse circulating circuit (ring delay circuit)
110
, the analog input voltage signal was supplied to the whole of circuits in the A/D converter
100
as its supply voltage. This affects the A/D converting operation in accuracy, particularly in linearity (non-linearity).
Due to this non-linearity, the input voltage dynamic range is limited if a sufficient accuracy is required.
FIG. 17
is a graphical drawing showing the linearity between measured voltages and the output data in the prior art A/D converter shown in FIG.
16
. With the measured voltage and the output data, a linearity error NL is calculated. As a result, if the input voltage range (FS: full scale) is limited from 2.0 V to 2.2 V, NL=0.4% FS. Accordingly, a sufficient input voltage range cannot be obtained without compensation.
The linearity error NL when the analog input voltage signal Vin varies from V
1
to V
2
is calculated with assumption that measured values are represented by A(Vi) when Vin =Vi (i=1, 2) as follows:
NL
=
A
[
V1
+
v2
2
]
-
A
(
V1
)
+
A
(
V2
)
2
A
(
V1
)
+
A
(
V2
)
(
1
)
Moreover, in the prior art a/c converter
100
, the analog input voltage signal Vin is used in the whole of the pulse phase difference coding circuit
2
. So, if the analog input voltage signal Vin varies rapidly, a considerable interval is necessary for stabilization of the voltage of the analog input voltage signal Vin supplied to the pulse phase difference coding circuit
2
.
Accordingly, if one of a plurality of image signals are successively supplied to the prior art A/D converter, the supply voltage at the phase difference coding circuit
2
would be converted in unstable conditions, so that stable A/D conversion could not be obtained.
SUMMARY OF THE INVENTION
The aim of the present invention is to provide a superior A/D converter.
According to the present invention, a first aspect of the present invention provides an A/D converter comprising: a pulse circulating circuit including a plurality of inverting circuits connected in series in a ring to generate and circulate a pulse for repeatedly outputting said pulse, one of said inverting circuits supplied with a first control signal to control generation of said pulse, each inverting circuit successively shifting an edge of said pulse to the next one of said inverting circuits with delay which varies in accordance with a supply voltage thereto; an input terminal for inputting and supplying an analog input voltage signal only to said inverting circuits as said supply voltage; a counter circuit for counting said pulse and in response to a second control signal and outputting binary count data; a pulse position detection circuit for detecting a position of one of said inverting circuits outputting an edge of said pulse and for, in response to a second control signal, encoding the position into binary encoded data; a control circuit for generating said first control signal to operate said pulse circulating circuit and after a predetermined interval from generation of said first control signal, generating said second control signal to detect said position; and an outputting circuit for outputting A/D conversion data including said binary count data as upper bits and said binary encoded data as lower bits, wherein each of said counter, said pulse position detection circuit, said control circuit, and said outputting circuit except said pulse circulating circuit, is supplied with a constant supply voltage.
According to the present invention, a second aspect of the present invention provides an A/D converter based on the first aspect, further comprises: input signal switching means for inputting either of said analog input voltage signal or a reference voltage in accordance with a selection signal; data storing means for storing said A/D conversion data when said reference signal is inputted to said input terminal through said input signal switching means; a dividing circuit for dividing said A/D conversion data when said analog input voltage signal is inputted to said input terminal through said input signal switching means by an output of said data storing means to output compensated A/D conversion data.
According to the present invention, a third aspect of the present invention provides an A/D converter based on the first aspect, wherein said control circuit comprises: a variable frequency oscillator for generating an oscillation signal of which frequency is controlled; and timing setting means for counting said oscillation signal and generating said first and second control signals in accordance with the counting result, said A/D converter further comprising: input signal switching means for inputting either of said analog input voltage signal, a first reference voltage, or a second reference voltage; first data storing means for storing said A/D conversion data when said first reference signal is inputted to said input terminal through said input signal switching means; second data storing means for storing said A/D conversion data when said second reference signal is inputted to said input terminal through said input signal switching means; oscillation frequency control means for obtaining a difference between outputs of said first and second storing means and controlling said frequency of said variable frequency oscillator to make said difference equal to a predetermined value; and deviati
Nishii Katsuyoshi
Watanabe Takamoto
Denso Corporation
Law Offices of David G. Posz
Young Brian
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