A/D converter

Details A/D converter A/D converter

1999-07-16

2001-05-08

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06229472

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to an A/D converter, more in particular to the A/D converter outputting a digital signal converted from an analog signal by sequentially changing reference voltages one after another input to a comparator.
(b) Description of the Related Art
An A/D converter (ADC) operating at high speed and with low power dissipation has been conventionally developed by employing CMOS technology for a purpose is of integration to an LSI. Conventionally, the A/D converter realized by the CMOS technology includes all-parallel type, serial-to-parallel type and pipeline type converters.
The all-parallel type A/D converter as described in ICD94-49 and JP-A-95-336225 is a system in which comparison between an analogue input and (2
N
−1) reference voltages is collectively conducted by employing (2
N
−1) comparators. Such an A/D converter is shown in a block diagram of FIG.
1
.
The A/D converter includes an input buffer (input amplifier)
15
to which an analogue signal Vin is input for driving a comparator array
18
, a resistor ladder
11
for generating (2
N
−1) reference voltages Vref
1
to Vrefn (n=2
N
−1) connected between a first reference source line VRT and a second reference source line VRB, the comparator array
18
having a number of comparators
17
to which the reference voltages Vref
1
to Vrefn from the resistor ladder
11
and an analogue signal Vin from the input buffer
15
are input, and an encoder to which outputs from the respective comparators
17
of the comparator array
18
are input. The respective comparators
17
includes a charge capacitor C having a first terminal connected to the input buffer
15
and to the corresponding reference voltage by switches SW
1
and SW
3
, respectively, and an amplifier AMP having an input connected to a second terminal of a charge capacitor C and an output connected to the input of the amplifier AMP by a switch SW
2
.
The input voltage Vin is supplied to the amplifiers AMP of the respective comparators
17
through the input buffer
15
. The switches SW
1
, SW
2
and SW
3
of the comparators
17
are controlled by clock signals. The switches SW
1
and SW
2
of the comparator
17
simultaneously become active at a high level of the clock signal &phgr;
1
and a charge corresponding to a difference between the input voltage Vin and an input offset voltage of the comparator AMP is charged in the charge capacitor C. When X&phgr;
1
(X&phgr;
1
is an inverted signal of &phgr;
1
) rises to a high level, the switches SW
1
and SW
2
turn off and the switch SW
3
turns on, the respective reference voltages Vref
1
to Vrefn are connected to the corresponding comparators
17
to perform comparison between the input voltage Vin and the corresponding reference voltages Vref
1
to Vrefn in the amplifier AMP of the respective comparators
17
. Since, at this moment, the input offset voltage of the amplifier AMP of the respective comparators
17
remains charged, no error generated even if the amplifier AMP includes the input offset voltage, thereby performing the accurate comparison between the voltages having only a small difference.
A conventional pipeline type A/D converter is described, for example, in IEEE 1991 Custom Integrated Circuits Conference 26.4, and operates an A/D sub-converter of low resolution by means of pipeline type processing.
FIG. 2
is a block diagram showing such an A/D converter. The A/D converter includes an S/H amplifier
20
which conducts a sampling of analogue input, holds thereof (S/H) and supplies its output signal to a subtracter
21
and to an AID sub-converter (ADSC
1
) which performs analogue-to-digital conversion of the signal held by the S/H amplifier
20
, a D/A converter (DAC
1
) for generating an analogue voltage corresponding to a digital output of ADSC
1
, an initial stage including the subtracter
21
for conducting subtraction between the held voltage and the voltage generated in DAC
1
, a plurality of interstage amplifiers
22
,
24
and
25
for amplifying the results of the subtraction and having the S/H function, a number of intermediate stages having a similar structure to that of the initial stage and receiving output signals of the respective interstage amplifiers
22
and
24
, an A/D sub-converter (ADSCn) for receiving an output signal from an interstage amplifier
25
of the final stage, and a digital correction circuit
26
for receiving data input from the ADSCs of the respective stages for correction to output a digital output Dout.
The throughput of the processing is increased in the A/D converter of
FIG. 2
due to pipeline-processing of the respective stages. The A/D sub-converter ADSC employed herein is basically the same as the all-parallel type A/D converter already mentioned, and the respective A/D converters are equipped with the comparators as mentioned above. Since, in this structure, the resolution of each stage is low and the number of the comparators is not so large, the power dissipation in the comparators is small and the power dissipation in the S/H amplifier and the interstage amplifiers of the respective stages is rather large.
In the pipeline system of
FIG. 2
, the serial-to-parallel type A/D converter adopts a two-stage structure. That is, the structure excluding a D/A converter (DAC
2
), the subtracter
23
, the interstage amplifiers
24
and
25
and an A/D sub-converter (ADSCn) from the structure of
FIG. 2
is employed. Also in this type of the A/D converter, the A/D sub-converter ADSC is basically the same as the all-parallel type A/D converter including the comparators.
Since the plurality of the comparators are connected in parallel to the output of the input amplifier
15
in the A/D converter of
FIG. 1
, the input capacitance of the comparator array observed from the input amplifier, of the S/H amplifier and of the interstage amplifier becomes as large as (charge capacitor C of comparator)×(the number of comparators) when the converter is employed as the A/D sub-converter in the pipeline type converters and in the serial-to-parallel type converters as well as when, of course, the converter is individually employed. Accordingly, the input buffer and the interstage amplifiers are required to have the high driving ability defectively resulting in the increase of power dissipation and of an occupied area.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention, in view of the above, to provide an A/D converter which enables reduction of power dissipation and of an occupied area even without employing a large input buffer and an interstage amplifier having a large driving ability.
The present invention provides, in a first aspect thereof, an A/D converter for converting an input analogue signal to a digital signal comprising: a reference voltage generator for generating a plurality of reference voltages; a comparator for comparing the plurality of the reference voltages with the input analogue signal, the comparator including a first switch having a first terminal connected to an analogue input terminal, an array of second switches each having a first terminal connected to the corresponding reference voltage and a second terminal connected in common to a second terminal of the first switch, a charge capacitor having a first terminal connected to second terminals of the first switch and of the array of the second switches, and an amplifier having an input connected to a second terminal of the charge capacitor and an output connected to the input of said comparator by a third switch; and an encoder for encoding an output signal of the comparator.
The present invention provides, in a second aspect thereof, an A/D converter including: first and second reference voltage generator for generating a plurality of first reference voltages and a plurality of second reference voltages, respectively; fourth and fifth switches each having a first terminal connected to an analogue input signal and to an inverted signal of the analogue input sign

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