A/D conversion technique using digital averages

Details A/D conversion technique using digital averages A/D conversion technique using digital averages

1999-11-03

2004-06-15

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06750799

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to the field of electronic signal conversion. More particularly, the present invention relates to the ability to more accurately represent a signal after an analog-to-digital conversion.
BACKGROUND OF THE INVENTION
An N-bit algorithmic (either pipeline or cyclic) analog-to-digital converter (ADC) may include J K-bit stages, where J*K=N. Each of the K-bit converter stages may have the general architecture of FIG.
1
. The input signal or output from a prior stage is denoted by Residue
i−1
and is connected to a sample-and-hold (S/H) circuit. The output of the S/H connects to a K-bit analog to digital subconverter (ADSC) and the positive input (+) of a summation component (&Sgr;). The output of the K-bit ADSC goes to a K-bit digital-to-analog converter (DAC), whose output goes to the negative input (−) of the summation component (&Sgr;). The output of the summation component (&Sgr;) then goes to an amplifier (A
v
) that has a gain of 2
K
. The output of the amplifier is the output of the stage and is denoted by Residue
i
.
Operationally, the K-bit analog to digital subconverter (ADSC) estimates the analog input, and the digital code is used by a local K-bit digital-to-analog converter (DAC) to create an analog estimate of the input voltage. This estimate is subtracted from the original analog input and the residue (an analog remainder) is passed on to the next stage for processing after being amplified by a gain of 2
K
. The resulting residue can be calculated from equation (1).
V
res
i
=2
K
(
V
res
i−1
−V
dac
i
)  (1)
In equation (1), Vres
i
denotes the residue voltage, K denotes the number of bits in the digital-to-analog converter, Vres
i−1
denotes the residue voltage from a prior stage or the input, and Vdac
i
represents the output voltage of the K-bit DAC.
The overall linearity of an algorithmic ADC is determined by the linearity of the DAC stage. An attractive solution, especially for high speed applications, is to use a 1-bit ADSC and DAC. With a single-bit decision, there is always a straight line that can be drawn between the positive and negative reference voltages. In this case, the ideal gain of the converter stage is 2.
The residue equation in the case of a 1-bit decision and a converter stage gain of 2 is given by equation (2), where the data (D
i
) can have one of two values, −
1
or +
1
.
V
res
i
=2
·V
res
i−1
−D
i
·V
ref  (2)
In equation (2), Vres
i
denotes the residue voltage, Vres
i−1
denotes the residue voltage from a prior stage or the input, D
i
denotes the data input and can at any given pipeline stage be either a−1 or +1 value, and Vref represents a reference voltage.
An ideal transfer characteristic from equation (2) is shown in FIG.
2
.
FIG. 3
illustrates an analog residue computation circuit that uses two phases to compute the residue. During phase
1
of a non-overlapping clock (the sample phase), switch S
1C
, holds the operational amplifier A
1
316
as a voltage follower and the input voltage Vres
i−1
304
minus any operational amplifier offset is sampled on the two capacitors C
1
and C
2
through switches S
1A
and S
1B
respectively. During phase
2
of the non-overlapping clock (the hold phase), one side of capacitor C
1
node
310
is connected to the operational amplifier output
318
through switch S
2B
and the other capacitor C
2
has one side node
308
connected to Di*Vref
306
through switch S
2A
. C
1
and C
2
can be defined as related by equation (3a).
C
1
=C
, and
C
2
=(1+&agr;
i
)
C
  (3a)
In equation (3a), C
1
and C
2
represent the capacitance, C represents a normalized capacitance equivalent to C
1
, and &agr;
i
denotes the capacitor mismatch between C
1
and C
2
.
The output voltage (the analog residue) is given by equation (3).
V
res=((2+&agr;
i
)·
V
res
i−1
−(1+&agr;
i
)·
D
i
·V
ref)·(1−&egr;
i
)+
V
ofs
i
  (3)
In equation (3); Vres
i
denotes the residue voltage, as denotes capacitor mismatch; Vres
i−1
denotes the residue voltage from a prior stage or the input; D
i
denotes the data input and can at any given pipeline stage be either a −1 or +1 value; Vref represents a reference voltage; &egr;
i
represents the error due to finite operational amplifier gain and settling; and Vofs
i
represents a total offset term due to the charge injection effects and operational amplifier offset.
These error terms affect the linearity of the overall converter. In particular, while the operational amplifier can be designed with high enough gain and speed such that the errors due to the operational amplifier are minimized, the capacitor mismatches have a technological limit that usually limits the accuracy to no better than about 10-bits. For higher resolution converters many calibration and/or correction techniques have been developed.
For certain applications, such as digital imaging, only the differential non-linearity (DNL) is critical. A commutated feedback capacitor switching technique has been developed to reduce the DNL even with relatively large capacitor mismatches. See Paul C. Yu and Hae-Seung Lee, “A Pipelined A/D Conversion Technique With Near-Inherent Monotonicity”, IEEE Transactions on Circuits and Systems II, vol. 42, pp. 500-502, July 1995; Paul C. Yu and Hae-Seung Lee, “A 2.5-V, 12-b, 5-MSample/s Pipelined CMOS ADC”, IEEE Journal of Solid-State Circuits, vol. 31, pp. 1854-1861, December 1996. This commutated feedback capacitor switching technique relies on the observation that the DNL is determined by the height of the transition gap in the transfer characteristic of FIG.
2
. At any particular conversion stage, the transition from Di=−1 to Di=+1 in the digital domain corresponds to a translation with +2Vref on the y-axis of the right half of the transfer characteristic. This effect is shown in FIG.
4
. If the transition gap height is very close to 2Vref, there may be no discontinuity in the equivalent transfer characteristic and the DNL will be small.
This commutated feedback capacitor switching technique achieves a very small DNL by swapping the capacitors used in the hold phase across the operational amplifier for the two regions of the transfer characteristic. Thus, neglecting the errors due to the operational amplifier finite gain and settling, the output voltage in the region Di=−1 is given by equation (4).
Vout
=
(
C
1
+
C
2
C
1
·
Vin
+
C
2
C
1
·
Vref
)
)
+
Vofs
i
(
4
)
The output voltage in the region Di=+1 is given by equation (5).
Vout
=
(
C
1
+
C
2
C
2
·
Vin
+
C
1
C
2
·
Vref
)
+
Vofs
i
(
5
)
In equation (4) and equation (5), Vout represents the output voltage, C
1
and C
2
represent capacitance, Vin represents the input voltage, Vref represents a reference voltage, and Vofs
i
represents a total offset term due to charge injection effects and operational amplifier offset.
From equations (4) and (5), the transition gap height can be derived as shown in equation (6), which is equal to 2 Vref up to a second error term.
Δ
⁢
 
⁢
Vout
=
(
C
1
C
2
+
C
2
C
1
)
·
Vref
≈
(
2
+
α
i
2
2
)
·
Vref
(
6
)
In equation (6) &Dgr;Vout
vin=0
denotes the transition gap height of Vout evaluated at Vin=0.
Although the commutated feedback capacitor switching technique improves the DNL to negligible values for practical purposes, it does not affect the integral non-linearity (INL), which remains largely determined by the capacitor matching. Certain applications, especially in communications, are very sensitive to INL errors, since these types of nonlinearities create distortion and tones in the received signal.
Thus, it is desirable to provide an analog-to-digital converter (ADC) with lowered INL errors.
SUMMARY OF THE INVENTION
The present invention includes a method and apparatus for an i

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