Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Reexamination Certificate
2003-07-09
2004-05-25
Tokar, Michael J. (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
C341S079000, C341S156000
Reexamination Certificate
active
06741192
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a serial/parallel A/D converter.
BACKGROUND OF THE INVENTION
With advances in digitization of signal processing in the field of communications and videos and enhancement of performances of video and communication devices, A/D converters as key devices for the digital signal processing are also required to achieve speedup and higher accuracy. As a basic configuration of a high-speed, high-accuracy A/D converter, there is a serial/parallel A/D converter (See U.S. Pat. No. 1,612,640).
Hereinafter, a construction and an operation of a conventional serial/parallel A/D converter will be described with reference to
FIGS. 12 and 13
.
Initially, the construction of the conventional serial/parallel A/D converter will be described with reference to FIG.
12
.
FIG. 12
is a diagram illustrating the construction of a conventional four-bit serial/parallel A/D converter.
As shown in
FIG. 12
, the conventional serial/parallel A/D converter comprises a reference resistor and switch array
12
which are connected between reference voltages
2
and
3
, a higher-order voltage comparator array
13
for deciding higher-order two bits, a higher-order code selecting circuit
14
which outputs higher-order code selection signals P
0
C-P
3
C on the basis of higher-order voltage comparison results C
1
C-C
3
C from the higher-order voltage comparator array
13
, a higher-order coding circuit
15
which outputs a two-bit higher-order binary code in accordance with the higher-order code selection signals, a lower-order voltage comparator array
16
for deciding lower-order two bits, a lower-order code selecting circuit
17
which outputs lower-order code selection signals P
0
F-P
3
F on the basis of lower-order voltage comparison results C
0
F-C
2
F from the lower-order voltage comparator array
16
, a lower-order coding circuit
18
which outputs a two-bit lower-order binary code in accordance with the lower-order code selection signals, a code compositing circuit
19
which performs a logic operation on the two-bit higher-order binary code and the two-bit lower-order binary code, thereby to output a four-bit digital signal, and a control signal generating circuit
21
which generates various kinds of control signals for controlling the operational timing of the serial/parallel A/D converter.
The reference resistor and switch array
12
includes a reference resistor
4
that comprises resistors R
01
-R
04
, R
11
-R
14
, R
21
-R
24
, and R
31
-R
34
, each having the same resistance value, for dividing the potential between the reference voltages
2
and
3
into 16 equal potentials; and a lower-order reference voltage selection switch
5
that comprises switches S
01
-S
03
, S
11
-S
13
, S
21
-S
23
, and S
31
-S
33
for selecting a lower-order reference voltage, which are provided at positions at which the potential is equally divided into sixteen, respectively.
One input terminal of each voltage comparator
6
constituting the higher-order voltage comparator array
13
is connected to points d
1
, d
2
or d
3
at which the potential difference between the reference voltages
2
and
3
of the reference resistor and switch array
12
is divided into four equal potentials, and the other input terminal is connected to an analog input terminal
1
. Output terminals of the higher-order voltage comparator array
13
are connected to the higher-order code selecting circuit
14
, and output terminals of the higher-order code selecting circuit
14
are connected to input terminals of the higher-order coding circuit
15
.
Further, one input terminal of each voltage comparator
6
constituting the lower-order voltage comparator array
16
is connected through the lower-order reference voltage selection switch
5
to the point at which the voltage between the respective points d
1
, d
2
and d
3
to which the respective voltage comparators
6
of the higher-order voltage comparator array
13
are connected, is divided into four equal potentials by the reference resistor
4
in the reference resistor and switch array
12
, and the other input terminal is connected to the analog input terminal
1
. Output terminals of the lower-order voltage comparator array
16
are connected to the lower-order code selecting circuit
17
, and output terminals of the lower-order code selecting circuit
17
are connected to the lower-order coding circuit
18
.
Output terminals of the higher-order coding circuit
15
and the lower-order coding circuit
18
are connected to the code compositing circuit
19
, and a four-bit digital output is obtained from an output terminal of the code compositing circuit
19
.
The control signal generating circuit
21
generates various kinds of control signals for controlling the operational timing of the serial/parallel A/D converter, i.e., a sampling signal, a higher-order comparison signal, a lower-order reference voltage decision signal, and a lower-order comparison signal, on the basis of a clock s
22
that is input from a clock terminal
22
. The sampling signal is input to the respective voltage comparators
6
of the higher-order voltage comparator array
13
and the lower-order voltage comparator array
16
, the higher-order comparison signal is input to the higher-order voltage comparator array
13
, the lower-order reference voltage decision signal is input to the higher-order voltage comparator array
13
, and the lower-order comparison signal is input to the lower-order voltage comparator array
16
, respectively. In
FIG. 12
, these control signals are not shown for the sake of simplification.
Next, the operation of the so-constructed serial/parallel A/D converter will be described with reference to FIG.
13
.
FIG. 13
is a timing chart illustrating the operation of the conventional serial/parallel A/D converter. In this figure, reference character (a) shows a clock, (b) shows a status of the higher-order voltage comparator array, (c) shows a status of the lower-order voltage comparator array, (d) shows a sampling signal, (e) shows a higher-order comparison signal, (f) shows a lower-order reference voltage decision signal, (g) shows a lower-order comparison signal, (h) shows a status of a lower-order reference voltage, (i) shows an analog input voltage, (j) shows the lower-order reference voltage, and (k) shows an output from the lower-order voltage comparator array. In the construction shown in
FIG. 12
, there are three lower-order reference voltages and the lower-order voltage comparator array have three outputs, while
FIG. 13
shows only one lower-order reference voltage and one output of the lower-order voltage comparator array for the sake of simplification.
Initially, in a sampling period (t1-t2 period), the higher-order voltage comparator array
13
and the lower-order voltage comparator array
16
are simultaneously connected to the analog input terminal
1
, and at a falling time of the sampling signal from the control signal generating circuit
21
, the respective comparators
6
of the higher-order voltage comparator array
13
and the lower-order voltage comparator array
16
hold an equal analog input voltage Vin of an analog input signal s
1
which is input from the analog input terminal
1
.
Then, in a higher-order comparison period (t2-t3 period), the respective voltage comparators
6
of the higher-order voltage comparator array
13
compare the analog input voltage Vin which is held in the sampling period, with respective higher-order reference voltages Vr
1
c
, Vr
2
c
and Vr
3
c
which are the voltage values at the points d
1
, d
2
and d
3
at which the potential difference between the reference voltages
2
and
3
is divided into four equal potentials. Then, at a falling time of the higher-order comparison signal from the control signal generating circuit
21
, the respective voltage comparators
6
of the higher-order voltage comparator array
13
output higher-order voltage comparison results C
1
C, C
2
C and C
3
C as the results of the comparison. Thereafter, the higher-order voltage comparison result
Murata Kenji
Nomasaki Daisuke
Matsushita Electric - Industrial Co., Ltd.
Nguyen John B
Parkhurst & Wendel L.L.P.
Tokar Michael J.
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